CY25818SCT CYPRESS [Cypress Semiconductor], CY25818SCT Datasheet - Page 3

• Manufacturer Part Number: CY25818SCT
• Description: Spread Spectrum Clock Generator
• Manufacturer: CYPRESS [Cypress Semiconductor]

Document #: 38-07362 Rev. *B
3-Level Digital Inputs
S0 digital input is designed to sense three logic levels desig-
nated as HIGH “1,” LOW “0,” and MIDDLE “M.” With this
3-Level digital input logic, the 3-Level logic is able to detect
three different logic levels.
The S0 pin includes an on-chip 20K (10K/10K) resistor divider.
No external application resistors are needed to implement
3-Level logic, as follows.
Logic Level “0”: 3-Level logic pin connected to GND.
Logic Level “M”: 3-Level logic pin left floating (no connection.)
Logic Level “1”: 3-Level logic pin connected to Vdd.
Figure 1 illustrates how to implement 3-Level Logic.
Table 3. Modulation Rate Divider Ratios
Maximum Ratings
Supply Voltage (Vdd): ..................................................+ 5.5V
Input Voltage Relative to Vdd:.............................. Vdd + 0.3V
Table 4. DC Electrical Characteristics Vdd = 3.3V ±10%, T
Vdd
V
V
V
V
V
V
V
C
C
I
I
I
Parameter
DD1
DD3
DD4
to V S S
INH
INM
INL
OH1
OH2
OL1
OL2
IN1
IN2
S 0
L O W (0 )
L O G IC
CY25818
CY25819
Product
V S S
Power Supply Range
Input HIGH Voltage
Input MIDDLE Voltage
Input LOW Voltage
Output HIGH Voltage
Output HIGH Voltage
Output LOW Voltage
Output LOW Voltage
Input Capacitance
Input Capacitance
Power Supply Current
Power Supply Current
Power Supply Current
Figure 1. 3-Level Logic
U N C O N N E C T E D
Description
[1, 2]
M ID D L E (M )
S 0
L O G IC
Input Frequency Range
S0 Input
S0 Input
S0 Input
I
I
I
I
X
All Digital Inputs
F
F
PD# = Vss
OH
OH
OL
OL
IN
IN
IN
=8 MHz, no load
=32 MHz, no load
= 4 ma, SSCLK Output
= 10 ma, SSCLK Output
(Pin 1) and X
= 4 ma, SSCLK and REFCLK
= 6 ma, SSCLK and REFCLK
to V D D
S 0
16–32 MHz
8–16 MHz
H IG H (H )
L O G IC
Conditions
V D D
OUT
A
(Pin 8)
= 0°C to +70°C and C
Modulation Rate
Spread Spectrum Clock Generators utilize frequency
modulation (FM) to distribute energy over a specific band of
frequencies. The maximum frequency of the clock (fmax) and
minimum frequency of the clock (fmin) determine this band of
frequencies. The time required to transition from fmin to fmax
and back to fmin is the period of the Modulation Rate, Tmod.
The Modulation Rates of SSCG clocks are generally referred
to in terms of frequency, and fmod = 1/Tmod.
The input clock frequency, fin, and the internal divider
determine the Modulation Rate.
In the case of CY25818/19 devices, the (Spread Spectrum)
Modulation Rate, fmod, is given by the following formula:
fmod = f
where fmod is the Modulation Rate, f
and DR is the Divider Ratio, as given in Table 3.
Input Voltage Relative to Vss:............................... Vss + 0.3V
Operating Temperature:................................... 0°C to + 70°C
Storage Temperature: ................................ –65°C to + 150°C
IN
/DR
0.85 Vdd
0.40 Vdd
Min.
2.97
0.0
2.4
2.0
6.0
3.5
–
–
–
–
–
L
= 15 pF (unless otherwise noted)
0.50 Vdd
Divider Ratio (DR)
Typ.
10.0
19.0
Vdd
150
3.3
0.0
7.5
4.5
–
–
–
–
IN
256
512
is the Input Frequency,
CY25818/19
0.60 Vdd
0.15 Vdd
Max.
3.63
12.5
23.0
Vdd
250
0.4
1.2
9.0
6.0
–
–
Page 3 of 7
Unit
mA
mA
mA
pF
pF
V
V
V
V
V
V
V
V
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