PLL601-12 PhaseLink (PLL), PLL601-12 Datasheet - Page 2

• Manufacturer Part Number: PLL601-12
• Description: , Odd Multipliers, 2 Outs,
• Manufacturer: PhaseLink (PLL)

FREQUENCY SELECTION TABLE
Note: Internal pull-ups default S3, S2, S1, and S0 to ‘1’ when not connected
PIN DESCRIPTION
47745 Fremont Blvd., Fremont, California 94538 TEL [phone] FAX [phone]
CLK2/REF_CLK
DRIVE_SEL
S3
REF_SEL
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
Name
XOUT
CLK1
GND
VDD
XIN
S0
S1
S2
S3
S2
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
Pin #
1,11
7,8
10
12
14
13
2
3
6
9
5
4
S1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
Dual Output PLL Clock with Selectable Odd Multiplier
Type
O
O
P
P
I
I
I
I
I
I
I
I
S0
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Crystal in connector.
Crystal out connector.
Selector pin. If DRIVE_SEL is ‘0’, outputs are at high drive. If ‘1’ or
not connected, outputs are standard drive (internal pull-up).
GND.
CLK1 output is the output of the reference frequency (crystal) after
multiplication through the Phase Locked Loop.
CLK2 or REF_CLK output (depending on REF_SEL). CLK2 is in
phase and at the same frequency as CLK1. REF_CLK provides the
same output as the crystal reference.
Selector pin. This pin if set to ‘0’ selects REF_CLK on pin 10. If
not connected, it defaults to ‘1’ (pin 10 = CLK2). Internal pull-up.
Multiplier selector pins. These pins have an internal pull-up that
will default SEL to ‘1’ when not connected to GND.
+3.3V VDD.
Xtal
Max
36
28
26
25
27
26
27
28
28
31
31
31
26
25
Xtal
Min
19
15
14
13
14
14
14
15
15
16
16
16
14
13
Description
Reserved
Reserved
X 4.25
X 11
X 12
X 12.5
X 5.75
X 3
X 11.5
X 5.5
X 2.75
X 5
X 2.5
X 10
X 6
X 6.25
Preliminary
Multiplier
PLL601-12
Rev 04/08/03 Page 2