74LVC2G14GF,132 NXP Semiconductors, 74LVC2G14GF,132 Datasheet - Page 10

• Manufacturer Part Number: 74LVC2G14GF,132
• Description: IC DUAL INV SCHMITT-TRIG 6-XSON
• Manufacturer: NXP Semiconductors
• Series: 74LVCr

Specifications of 74LVC2G14GF,132

• Number Of Circuits: 2
• Logic Type: Inverter with Schmitt Trigger
• Package / Case: 6-XSON, SOT891
• Number Of Inputs: 1
• Current - Output High, Low: 32mA, 32mA
• Voltage - Supply: 1.65 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Logic Family: LVC
• High Level Output Current: - 32 mA
• Low Level Output Current: 32 mA
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1.65 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 1.8 V, 2.5 V, 3.3 V, 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LVC2G14GF-H; 74LVC2G14GF-H; 935282433132

NXP Semiconductors
15. Application information
74LVC2G14
Product data sheet
Fig 12. Average I
Fig 13. Relaxation oscillator
(1) Positive-going edge.
(2) Negative-going edge.
Linear change of V
f
=
1
-- -
T
≈
---------------------
0.8 RC
CC
×
1
as a function of V
The slow input rise and fall times cause additional power dissipation, which can be
calculated using the following formula:
P
ΔI
An example of a relaxation circuit using the 74LVC2G14 is shown in
add
P
f
t
t
ΔI
CC(AV)
I
i
r
f
between 0.8 V to 2.0 V. All values given are typical unless otherwise specified.
add
= input frequency (MHz);
= input fall time (ns); 90 % to 10 %;
= input rise time (ns); 10 % to 90 %;
CC(AV)
= f
= additional power dissipation (μW);
i
differs with positive or negative input transitions, as shown in
ΔI
× (t
(mA)
CC(AV)
= average additional supply current (μA).
r
50
40
30
20
10
× ΔI
0
2
CC
All information provided in this document is subject to legal disclaimers.
CC(AV)
Rev. 5 — 29 October 2010
+ t
3
f
× ΔI
C
CC(AV)
R
4
Dual inverting Schmitt trigger with 5 V tolerant input
) × V
mna035
CC
5
(1)
(2)
V
where:
CC
mnb086
(V)
6
74LVC2G14
Figure
Figure
© NXP B.V. 2010. All rights reserved.
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