A1240A-1CQ176B ACTEL [Actel Corporation], A1240A-1CQ176B Datasheet - Page 18

• Manufacturer Part Number: A1240A-1CQ176B
• Description: ACT2 Family FPGAs
• Manufacturer: ACTEL [Actel Corporation]

A 12 80 A Ti m i ng Ch a r ac t e r i s t i cs
(Worst-Case Commercial Conditions, V
18
Logic Module Propagation Delays
Parameter
t
t
t
t
Predicted Routing Delays
t
t
t
t
t
Sequential Timing Characteristics
t
t
t
t
t
t
t
t
t
t
t
f
Notes:
1.
2.
3.
4.
PD1
CO
GO
RS
RD1
RD2
RD3
RD4
RD8
SUD
HD
SUENA
HENA
WCLKA
WASYN
A
INH
INSU
OUTH
OUTSU
MAX
Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating device
For dual-module macros, use t
performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route timing is
based on actual routing delay measurements performed on the device prior to shipment.
Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be obtained
from the DirectTime Analyzer utility.
Setup and hold timing parameters for the Input Buffer Latch are defined with respect to the PAD and the D input. External setup/hold
timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to the G input
subtracts (adds) to the internal setup (hold) time.
Description
Single Module
Sequential Clk to Q
Latch G to Q
Flip-Flop (Latch) Reset to Q
FO=1 Routing Delay
FO=2 Routing Delay
FO=3 Routing Delay
FO=4 Routing Delay
FO=8 Routing Delay
Flip-Flop (Latch) Data Input
Setup
Flip-Flop (Latch) Data Input Hold
Flip-Flop (Latch) Enable Setup
Flip-Flop (Latch) Enable Hold
Flip-Flop (Latch) Clock Active
Pulse Width
Flip-Flop (Latch) Asynchronous
Pulse Width
Flip-Flop Clock Input Period
Input Buffer Latch Hold
Input Buffer Latch Setup
Output Buffer Latch Hold
Output Buffer Latch Setup
Flip-Flop (Latch) Clock
Frequency
2
PD1
+ t
1
3,4
RD1
+ t
PDn
, t
CO
CC
+ t
RD1
= 4.75 V, T
Min.
11.7
0.4
5.5
5.5
0.0
0.4
0.0
0.4
0.0
0.8
0.0
+ t
‘–2’ Speed
PDn
v4.0
, or t
Max.
85.0
3.8
3.8
3.8
3.8
1.7
2.5
3.0
3.7
6.7
PD1
J
+ t
= 70°C)
RD1
+ t
Min.
13.3
0.4
0.0
0.9
0.0
6.0
6.0
0.0
0.4
0.0
0.4
SUD
‘–1’ Speed
, whichever is appropriate.
Max.
75.0
4.3
4.3
4.3
4.3
2.0
2.8
3.4
4.2
7.5
A C T
Min.
18.0
0.5
0.0
1.0
0.0
7.0
7.0
0.0
0.5
0.0
0.5
‘Std’ Speed
™
2 F a m il y F P GA s
Max.
50.0
5.0
5.0
5.0
5.0
2.3
3.3
4.0
4.9
8.8
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns