pll2109x Samsung Semiconductor, Inc., pll2109x Datasheet - Page 6

• Manufacturer Part Number: pll2109x
• Description: Description = PLL2109X 100MHz ~ 500MHz FSPLL ;; Function = FSPLL ;; Configuration = 100~500MHz FSPLL ;; Library Type = STD150 ;; Characteristic = 1.2V/3mA
• Manufacturer: Samsung Semiconductor, Inc.

PLL2109X (PRELIMINARY)
FUNCTIONAL DESCRIPTION
A PLL is the circuit synchronizing an output signal (generated by a VCO) with a reference or input signal in
frequency as well as in phase. The pll2109x can provide frequency multiplication capabilities, but does not
support functions such as deskew and phase synchronization between Fin and Fout.
PLL2109X consists of the following basic blocks.
— The phase frequency detector (PFD) detects the phase difference between the reference clock and feedback
— The loop filter suppresses high frequency components in the charge pump voltage (Vctrl), allowing the dc
— The voltage-controlled oscillator generates the clock signal proportional to control voltage.
— Don't set the value P or M to all zero, that is 000000 / 00000000.
— The range of P and M: 1
— The M and P must be selected considering stability and VCO range.
Digital Data Format:
NOTE: M[7] - M[0]: main-divider
Important Notice:
6
M7, M6, M5, M4, M3, M2, M1, M0
clock, then generates UP/DOWN error signals. If reference clock leads or lags feedback clock, the charge
pump charges or discharges the following loop filter according to UP/DOWN signal.
value to control the VCO frequency.
Required frequency is produced by appropriate selection of P, M and S dividers.
Fout = Fin
m = M+8 , p = P+2, s = 1, 2, 4, 8
VCO output frequency range of pll2109x is from 200MHz to 500MHz.
P[5] - P[0]: pre-divider
S[1] - S[0]: post-scaler
Main Divider
m/(p
Please contact SEC application engineer for proper selection of M, P, S values.
s)
P
1
0
1
62, 1
M
S
P
248
3
62
M
P5, P4, P3, P2, P1, P0
248
Pre Divider
100MHZ ~ 500MHZ FSPLL
Post Scaler
S1, S0