ssd1322z Newhaven Display International, Inc, ssd1322z Datasheet - Page 19

• Manufacturer Part Number: ssd1322z
• Description: 480 X 128, Dot Matrix High Power Oled/pled Segment/common Driver With Controller
• Manufacturer: Newhaven Display International, Inc

Note
(1)
(2)
(3)
(4)
Figure 13-2 for Form
In order to match the operating frequency of display RAM with that of the microprocessor, some pipeline
processing is internally performed which requires the insertion of a dummy read before the first actual display
data read. This is shown in Figure 8-4.
8.1.3
The serial interface consists of serial clock SCLK, serial data SDIN, D/C#, CS#. In SPI mode, D0 acts as
SCLK, D1 acts as SDIN. For the unused data pins, D2 should be left open. The pins from D3 to D7, E and
R/W# can be connected to an external ground.
Note
(1)
(2)
SDIN is shifted into an 8-bit shift register on every rising edge of SCLK in the order of D7, D6, ... D0. D/C#
is sampled on every eighth clock and the data byte in the shift register is written to the Graphic Display Data
RAM (GDDRAM) or command register in the same clock.
SSD1322
Databus
H stands for HIGH in signal
L stands for LOW in signal
Refer
WR#
L stands for LOW in signal
↑ stands for rising edge of signal
RD#
H stands for HIGH in signal
to
MCU Serial Interface (4-wire SPI)
Rev 0.10
Figure 8-4 : Display data read back procedure - insertion of dummy read
1
Write column
8080-Series MPU Parallel Interface Timing Characteristics
address
Function
Write command
Write data
N
P 19/56 Apr 2008
Function
Write command
Read status
Write data
Read data
Table 8-3 : Control pins of 8080 interface (Form 1)
Table 8-4 : Control pins of 4-wire Serial interface
Dummy read
E(RD#)
Tie LOW
Tie LOW
RD#
H
↑
H
↑
R/W#(WR#)
Read 1st data
Tie LOW
Tie LOW
WR#
↑
H
↑
H
n
CS#
L
L
L
L
CS#
L
L
Read 2nd data
D/C#
D/C#
L
L
H
H
n+1
H
L
D0
↑
↑
Read 3rd data
n+2
Solomon Systech