DS1775R/TR1 DALLAS [Dallas Semiconductor], DS1775R/TR1 Datasheet - Page 4

• Manufacturer Part Number: DS1775R/TR1
• Description: SOT23-5 Digital Thermometer and Thermostat
• Manufacturer: DALLAS [Dallas Semiconductor]

The resolution of the temperature conversion is configurable (9, 10, 11, or 12 bits), with 9–bit readings
the default state. This equates to a temperature resolution of 0.5 C, 0.25 C, 0.125 C, or 0.0625 C.
Following each conversion, thermal data is stored in the thermometer register in two’ s complement
format; the information can be retrieved over the 2–wire interface with the device pointer set to the
temperature register. Table 2 describes the exact relationship of output data to measured temperature. The
table assumes the DS1775 is configured for 12–bit resolution; if the device is configured in a lower
resolution mode, those bits will contain zeros. The data is transmitted serially over the 2–wire serial
interface, MSb first. The MSb of the temperature register contains the “sign” (S) bit, denoting whether the
temperature is positive or negative. For Fahrenheit usage, a lookup table or conversion routine must be
used.
Temperature/Data Relationships Table 2
OPERATION–Thermostat Control
In its comparator operating mode, the DS1775 functions as a thermostat with programmable hysteresis, as
shown in Figure 2. When the DS1775’ s temperature meets or exceeds the value stored in the high
temperature trip register (T
output becomes active and stays active until the first time that the temperature falls below the temperature
stored in the low temperature trigger register (T
obtained. The DS1775 powers up in the comparator mode with T
used as a standalone thermostat (no 2–wire interface required) with those setpoints.
In the interrupt mode, the O.S. output will first become active following the programmed number of
consecutive conversions above T
shutdown mode or by reading any register (temperature, configuration, T
Following a clear, a subsequent fault can only occur if consecutive conversions fall below T
interrupt/clear process is thus cyclical (T
of multiple consecutive T
function. The same situation applies to multiple consecutive T
MSb
2
S
-1
+25.0625 C
-25.0625 C
+10.125 C
-10.125 C
+125 C
TEMP
+0.5 C
-0.5 C
-55 C
+0 C
2
2
-2
6
2
2
-3
5
OS
OS
) a consecutive number of times, as defined by the configuration register, the
violations will activate O.S., even if each fault is separated by a clearing
OS
2
2
(UNIT = C)
. The fault can only be cleared by either setting the DS1775 in a
-4
0111 1101 0000 0000
0000 1010 0010 0000
0000 1010 0010 0000
0000 0000 1000 0000
0000 0000 0000 0000
1111 1111 1000 0000
1111 0101 1110 0000
1110 0110 1111 0000
1100 1001 0000 0000
DIGITAL OUTPUT
4
OS
, clear, T
(Binary)
2
0
3
4 of 13
HYST
HYST
). In this way, any amount of hysteresis may be
, clear, T
2
0
2
HYST
OS
events.
OS
, clear, T
2
0
1
=80 C and T
DIGITAL OUTPUT (Hex)
OS
HYST
LSb
, or T
2
0
0
, clear, ...). Only the first
HYST
HYST
7D00h
0A20h
F5E0h
E6F0h
C900h
FF80h
1910h
0080h
0000h
=75 C and can be
102299
) on the device.
MSB
LSB
HYST
DS1775
. This