DS1743P DALLAS [Dallas Semiconductor], DS1743P Datasheet - Page 3

• Manufacturer Part Number: DS1743P
• Description: Y2KC Nonvolatile Timekeeping RAM
• Manufacturer: DALLAS [Dallas Semiconductor]

DS1743 BLOCK DIAGRAM Figure 1
DS1743 TRUTH TABLE Table 1
SETTING THE CLOCK
As shown in Table 2, bit 7 of the century register is the write bit. Setting the write bit to a 1, like the read
bit, halts updates to the DS1743 registers. The user can then load them with the correct day, date and time
data in 24-hour BCD format. Resetting the write bit to a 0 then transfers those values to the actual clock
counters and allows normal operation to resume.
STOPPING AND STARTING THE CLOCK OSCILLATOR
The clock oscillator may be stopped at any time. To increase the shelf life, the oscillator can be turned off
to minimize current drain from the battery. The
Table 2. Setting it to a 1 stops the oscillator.
FREQUENCY TEST BIT
As shown in Table 2, bit 6 of the day byte is the frequency test bit. When the frequency test bit is set to
logic 1 and the oscillator is running, the LSB of the seconds register will toggle at 512 Hz. When the
seconds register is being read, the DQ0 line will toggle at the 512 Hz frequency as long as conditions for
access remain valid (i.e.,
stable).
V
V
V
SO
CC
CC
<V
<V
V
>V
CC
CC
SO
<V
<V
PF
PF
PF
V
V
V
V
CE
X
X
X
IH
IL
IL
IL
CE
CE2
V
V
V
V
X
X
X
low,
IH
IH
IH
IL
OE
V
V
OE
X
X
X
X
X
IL
IH
low,
WE
V
V
V
X
X
X
X
IH
IH
IL
WE
DESELECT
DESELECT
DESELECT
DESELECT
OSC
high, and address for seconds register remain valid and
3 of 17
WRITE
MODE
READ
READ
bit is the MSB (bit 7) of the seconds registers, see
DATA OUT
DATA IN
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
HIGH-Z
DQ
DATA RETENTION
CMOS STANDBY
STANDBY
STANDBY
POWER
ACTIVE
ACTIVE
ACTIVE
MODE
DS1743/DS1743P