UPD72001-A8 NEC [NEC], UPD72001-A8 Datasheet - Page 9

• Manufacturer Part Number: UPD72001-A8
• Description: MULTI-PROTOCOL SERIAL CONTROLLERS
• Manufacturer: NEC [NEC]

(9) D7 through D0 (Data Bus) ... I/O
(10) INT (Interrupt) ... Output (open drain)
(11) INTAK (Interrupt Acknowledge) ... Input
(12) PRI (Priority Input) ... Input
Table 1-2 shows the selection operations by WR, RD, B/A, and C/D.
These pins constitute a three-state 8-bit bidirectional data bus. This data bus is connected to the data bus of
the host processor to transfer control words, status, and transmit/receive data.
This pin outputs an interrupt request signal. If an interrupt occurs in the MPSC, it goes low (active). Because
this is an open-drain output pin, it must be pulled up.
This pin inputs a signal to acknowledge interrupt request signals issued by the MPSC. This pin is active-low.
This pin is used when the vector mode (CR2A: D7 = “1”) is selected, and must be pulled up to “H” when the non-
vector mode (CR2A: D7 = “0”) is selected.
This input pin is used for an interrupt generation request signal and for an output control signal for interrupt vectors.
In the normal operation mode, this pin provides an interrupt generation control function. During the INTAK
sequence, it provides an output control function for interrupt vectors. How this pin is used differs depending on
the interrupt mode.
(a) In vector mode (CR2A: D7 = “1”)
In the normal operation mode, the PRI pin is used to control generation of interrupts. When interrupt vector
output mode of Type A-3 or Type B-2 (CR2A: D5, D4, D3 = “0, 1, 0” or “1, 0, 0”) is selected, interrupts can
be generated regardless of whether the PRI pin is “L” or “H”.
If any other interrupt vector output mode is selected, the PRI pin must be kept “L” to enable generation of
interrupts.
During the INTAK sequence, an interrupt vector is output if “L” is input to the PRI pin in any interrupt vector
output mode, and output of the interrupt vector is disabled if “H” is input to PRI.
WR
H
H
H
L
L
L
RD
H
H
H
L
L
L
B/A
H
H
H
H
L
L
L
L
C/D
H
H
L
L
Table 1-2. MPSC Control Signals and Operations
Channel A
Channel B
Channel A
Channel B
Channel A
Channel B
Channel A
Channel B
High-impedance state or INTAK sequence
Setting prohibited
Reads receive data from R
Writes control register
Reads status register
Writes transmit data to T
Operation
X
X
buffer
buffer
PD72001-11, 72001-A8
: Don’s Care
9