UPD705100GJ-100-8 NEC [NEC], UPD705100GJ-100-8 Datasheet - Page 14

• Manufacturer Part Number: UPD705100GJ-100-8
• Description: V830TM 32-BIT MICROCONTROLLER
• Manufacturer: NEC [NEC]

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4. 16-BIT BUS MODE
mode, the low-order 16 bits (D0-D15) of the data bus are valid, BE2/BH acts as BH and BE3/A1 acts as A1. The high-
order 16 bits (D16-D31) of the data bus enter the high-impedance state.
4.1 16-Bit Bus Sizing
I/O space, data can be transferred using only the low-order 16 bits of the 32-bit data bus.
In 16-bit bus mode, D16-D31 are all set to the high-impedance state and BE0, BE1, BH, and A1 are output in a way
suited to a 16-bit bus system. Connection to D16-D31 is not necessary. The SIZ16B input can be changed only when
the V830 is reset. It cannot be changed at any other time.
4.1.1 Byte/halfword access
(1) Upper halfword
If the SIZ16B input, sampled at reset, is active, the external bus width becomes 16 bits (16-bit bus mode). In this
The V830 has a bus sizing function by which, to enable access from the data bus to 16 bits of memory or the
When the SIZ16B input is activated upon a reset, the external data bus width becomes 16 bits (16-bit bus mode).
Bus cycles in either of two bus states (Ta and Ts) are used for byte/halfword access.
During read cycles, data is read from D0-D15.
During write cycles, D16-D31 data read from the write buffer is output to D0-D15.
Figure 4-1 illustrates the operation for upper halfword access. In this figure, B indicates the upper halfword (high-
order 16 bits of the word).
operation
Internal
unit
Read cycle
16
15
31
Read buffer
0
B
Figure 4-1. Upper Halfword Access
31
16
15
0
B
Data bus
operation
Internal
unit
Write cycle
Write buffer
16
15
31
0
B
16
15
31
0
B
Data bus
PD705100