DS2482-101_12 MAXIM [Maxim Integrated Products], DS2482-101_12 Datasheet - Page 4

• Manufacturer Part Number: DS2482-101_12
• Description: Single-Channel 1-Wire Master with Sleep Mode
• Manufacturer: MAXIM [Maxim Integrated Products]

Single-Channel 1-Wire Master with Sleep Mode
ELECTRICAL CHARACTERISTICS (continued)
(V
Note 1:
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
Note 10: All I
Note 11: Applies to SDA, SCL, and AD0.
Note 12: The input/output pins of the DS2482-101 do not obstruct the SDA and SCL lines if V
Note 13: The DS2482-101 provides a hold time of at least 300ns for the SDA signal (referred to the V
Note 14: The maximum t
Note 15: A fast-mode I
Note 16: C
4
Input Current Each Input/Output
Pin with an Input Voltage
Between 0.1 x V
0.9 x V
Input Capacitance
SCL Clock Frequency
Hold Time (Repeated) START
Condition (After this period, the
first clock pulse is generated.)
Low Period of the SCL Clock
High Period of the SCL Clock
Setup Time for a Repeated
START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a STOP
and START Condition
Capacitive Load for Each Bus
Line
Oscillator Warmup Time
CC
_______________________________________________________________________________________
= 2.9V to 5.5V, T
CC(MAX)
PARAMETER
Operating current with 1-Wire write-byte sequence followed by continuously reading the Status Register at 400kHz in overdrive.
With standard speed, the total capacitive load of the 1-Wire bus should not exceed 1nF. Otherwise, the passive pullup on
threshold V
not exceed 300pF.
Active pullup guaranteed to turn on between V
Active or resistive pullup choice is configurable.
Except for t
these parameters is found to be off the typical value, it is safe to assume that all these parameters deviate from their typi-
cal value in the same direction and by the same degree.
These values apply at full load, i.e., 1nF at standard speed and 0.3nF at overdrive speed. For reduced load, the pulldown
slew rate is slightly faster.
Fall time high-to-low (t
I
sleep mode.
Guaranteed by design and not production tested.
bridge the undefined region of the falling edge of SCL.
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line t
250 = 1250ns (according to the standard-mode I
Bus Specification Version 2.1 are allowed.
2
C communication should not take place for the max t
B
—Total capacitance of one bus line in pF. If mixed with high-speed-mode devices, faster fall times according to I
2
C timing values are referred to V
CC(MAX)
IL1
A
F1
= -40°C to +85°C.)
2
, all 1-Wire timing specifications and t
C bus device can be used in a standard-mode I
may not be reached in the available time. With overdrive speed, the capacitive load on the 1-Wire bus must
and
HD:DAT
F1
need only be met if the device does not stretch the low period (t
) is derived from PD
SYMBOL
t
t
t
OSCWUP
t
t
t
HD:STA
HD:DAT
SU:STO
SU:STA
SU:DAT
t
t
f
HIGH
t
LOW
SCL
BUF
C
C
I
I
B
I
IH(MIN)
(Notes 11, 12)
(Note 11)
(Notes 13, 14)
(Note 15)
(Note 16)
(Note 8)
SRC
and V
IL1(MAX)
, referenced from 0.9 x V
2
C bus specification) before the SCL line is released.
IL(MAX)
APUOT
CONDITIONS
OSCWUP
and V
levels.
are derived from the same timing circuit. Therefore, if one of
IH1(MIN)
2
or t
C bus system, but the requirement t
SWUP
.
CC
time following a power-on reset or a wakeup from
to 0.1 x V
CC
CC
MIN
is switched off.
LOW
250
-10
0.6
1.3
0.6
0.6
0.6
1.3
0
.
IH(MIN)
) of the SCL signal.
R(MAX)
TYP
of the SCL signal) to
SU:DAT
+ t
SU:DAT
MAX
+10
400
400
100
0.9
10
≥ 250ns must
= 1000 +
UNITS
kHz
2
μA
pF
μs
μs
μs
μs
μs
ns
μs
μs
pF
μs
C-