DS2482-101_12 MAXIM [Maxim Integrated Products], DS2482-101_12 Datasheet - Page 15

• Manufacturer Part Number: DS2482-101_12
• Description: Single-Channel 1-Wire Master with Sleep Mode
• Manufacturer: MAXIM [Maxim Integrated Products]

Figure 7. I
The I
(SCL) for communication. Both SDA and SCL are bidi-
rectional lines, connected to a positive supply voltage
through a pullup resistor. When there is no communica-
tion, both lines are high. The output stages of devices
connected to the bus must have an open drain or open
collector to perform the wired-AND function. Data on
the I
100kbps in standard mode and up to 400kbps in fast
mode. The DS2482-101 works in both modes.
A device that sends data on the bus is defined as a
transmitter, and a device receiving data is defined as a
receiver. The device that controls the communication is
called a master. The devices that are controlled by the
master are slaves. To be individually accessed, each
device must have a slave address that does not conflict
with other devices on the bus.
Data transfers can be initiated only when the bus is not
busy. The master generates the serial clock (SCL), con-
trols the bus access, generates the START and STOP
conditions, and determines the number of data bytes
transferred between START and STOP (Figure 7). Data
is transferred in bytes with the most significant bit being
SDA
SCL
Single-Channel 1-Wire Master with Sleep Mode
2
2
C bus uses a data line (SDA) plus a clock signal
C bus can be transferred at rates of up to
IDLE
2
C Protocol Overview
CONDITION
START
______________________________________________________________________________________
ADDRESS
MSB FIRST
SLAVE
1–7
General Characteristics
R/W
8
I 2 C Interface
ACK
9
MSB
1–7
REPEATED IF MORE BYTES
ARE TRANSFERRED
DATA
LSB
transmitted first. After each byte follows an acknowledge
bit to allow synchronization between master and slave.
The slave address to which the DS2482-101 responds
is shown in Figure 8. The logic state at the address pin
AD0 determines the value of the address bit A0. The
address pin allows the device to respond to one of two
possible slave addresses. The slave address is part of
the slave address/control byte. The last bit of the slave
address/control byte (R/W) defines the data direction.
When set to 0, subsequent data flows from master to
slave (write access); when set to 1, data flows from
slave to master (read access).
Figure 8. DS2482-101 Slave Address
8
ACK
9
MSB
A6
0
A5
0
MSB
7-BIT SLAVE ADDRESS
1–7
A4
1
DATA
A3
1
LSB
8
A2
0
PIN STATE
AD0
A1
0
NACK
ACK/
9
AD0
Slave Address
A0
READ OR WRITE
DETERMINES
STOP CONDITION
REPEATED START
R/W
15