ch7301a ETC-unknow, ch7301a Datasheet - Page 20

• Manufacturer Part Number: ch7301a
• Description: Chrontel Ch7301 Dvi Output Device
• Manufacturer: ETC-unknow

CHRONTEL
20
Input Clock Register
Bits 3-0 of register IC controls the delay applied to the XCLK signal before latching input data.
GPIO Control Register
Bit 2 of register GPIO enables the hot plug interrupt detection signal to be output from the P-Out pin. A value of ‘1’
allows the hot plug detect circuit to pull the TLDET* pin low when a change of state has taken place on the hot plug
detect pin. A value of ‘0’ disables the interrupt signal.
Bit 3 of register GPIO resets the hot plug detection circuitry. A value of ‘1’ causes the CH7301 to release the
TLDET* pin. When a hot plug interrupt is asserted by the CH7301, the CH7301 driver should read register 20h to
determine the state of the DVI termination. After having read this register, the HPIR bit should be set high to reset
the circuitry, and then set low again.
Bits 5-4 of register GPIO control the GPIO pins. When the corresponding GOENB bits are low, these register
values are driven out of the corresponding GPIO pins. When the corresponding GOENB bits are high, these register
values can be read to determine the level forced into the corresponding GPIO pins.
Bits 7-6 of register GPIO control the direction of the GPIO pins. A value of ‘1’ sets the corresponding GPIO pin to
an input, and a value of ‘0’ sets the corresponding pin to an output.
DEFAULT:
DEFAULT:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
GOENB1 GOENB0 GPIOL1 GPIOL0
Reserved Reserved Reserved Reserved XCMD3 XCMD2 XCMD1
R/W
R/W
7
1
7
1
R/W
R/W
6
1
6
0
R/W
R/W
5
0
5
0
R/W
R/W
4
0
4
0
HPIR
R/W
R/W
3
0
3
1
HPIE Reserved
201-0000-036 Rev 1.1, 3/20/2000
R/W
R/W
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
2
0
2
0
R/W
R/W
CH7301A
1
0
1
0
IC
1Dh
8
GPIO
1Eh
8
Reserved
XCMD0
R/W
R/W
0
0
0
0