ch7301a ETC-unknow, ch7301a Datasheet - Page 19

• Manufacturer Part Number: ch7301a
• Description: Chrontel Ch7301 Dvi Output Device
• Manufacturer: ETC-unknow

CHRONTEL
Table 8: IIC Register Map w/o Macrovision
All register bits not defined in the register map are reserved bits, and should be left at the default value.
Clock Mode Register
Bit 0 of register CM signifies the XCLK frequency. A value of ‘0’ is used when the XCLK is at the pixel frequency
(duel edge clocking mode) and a value of ‘1’ is used when the XCLK is twice the pixel frequency (single edge
clocking mode).
Bit 2 of register CM controls the phase of the XCLK clock input to the CH7301. A value of ‘1’ inverts the XCLK
signal at the input of the device. This control is used to select which edge of the XCLK signal to use for latching
input data.
201-0000-036 Rev 1.1, 3/20/2000
DEFAULT:
Register
1Ch
1Dh
1Eh
1Fh
20h
21h
22h
31h
32h
33h
35h
36h
37h
48h
49h
4Ah
4Bh
SYMBOL:
TYPE:
BIT:
Bit 7
GOENB1
IBS
HPIE2
Reserved
Reserved
TPPD3
TPVCO7
DVID2
TPLPF3
TPVCO10 TPVCO9
DVIP
VID7
DID7
7
Bit 6
GOENB0
Reserved
Reserved
Reserved
Reserved
TPPD2
TPVCO6
DVID1
TPLPF2
DVIL
VID6
DID6
6
Bit 5
GPIOL1
Reserved
DVIT
Reserved
TPPD1
TPVCO5
DVID0
TPVT5
TPLPF1
TPVCO8
Reserved
VID5
DID5
5
Bit 4
GPIOL0
Reserved
SYNCO1
BCOEN
TPPD0
TPVCO4
DVII
TPVT4
TPLPF0
ResetIB
DACPD3
VID4
DID4
4
Bit 3
Reserved
XCMD3
HPIR
Reserved
DACT2
SYNCO0
BCOP
CTL3
TPVCO3
TPVT3
ResetDB
DACPD2
VID3
DID3
Reserved
R/W
3
0
Bit 2
MCP
XCMD2
HPIE
IDF2
DACT1
DACG1
BCO2
CTL2
TPVCO2
TPVT2
RSA
DACPD1
VID2
DID2
MCP Reserved
R/W
Symbol:
Address:
Bits:
2
0
Bit 1
Reserved
XCMD1
Reserved
IDF1
DACT0
DACG0
BCO1
CTL1
TPVCO1
TPCP1
TPVT1
TSTP1
DACPD0
VID1
DID1
R/W
CH7301A
1
0
Bit 0
XCM
XCMD0
Reserved
IDF0
SENSE
DACBP
BCO0
CTL0
TPVCO0
TPCP0
TPVT0
TSTP0
FPD
VID0
DID0
CM
1Ch
2
XCM
R/W
19
0
0