74AUP1G240GW,125 NXP Semiconductors, 74AUP1G240GW,125 Datasheet
74AUP1G240GW,125
Specifications of 74AUP1G240GW,125
74AUP1G240GW-G
935279061125
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74AUP1G240GW,125 Summary of contents
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Low-power inverting buffer/line driver; 3-state Rev. 2 — 13 September 2010 1. General description The 74AUP1G240 provides the single inverting buffer/line driver with 3-state output. The 3-state output is controlled by the output enable input (OE). A HIGH level ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information Type number Package Temperature range Name −40 °C to +125 °C 74AUP1G240GW −40 °C to +125 °C 74AUP1G240GM −40 °C to +125 °C 74AUP1G240GF −40 °C to +125 °C 74AUP1G240GN −40 °C to +125 °C 74AUP1G240GS 4. Marking Table 2. Marking ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning 74AUP1G240 GND 001aac525 Fig 4. Pin configuration SOT353-1 6.2 Pin description Table 3. Pin description Symbol Pin TSSOP5 GND n. Functional description [1] Table 4. Function table Input [ HIGH voltage level LOW voltage level Don’t care high-impedance OFF-state. 74AUP1G240 Product data sheet Low-power inverting buffer/line driver ...
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... NXP Semiconductors 8. Limiting values Table 5. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Symbol Parameter V supply voltage CC I input clamping current IK V input voltage I I output clamping current OK V output voltage O I output current ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I OFF-state output current OZ I power-off leakage current OFF ΔI additional power-off OFF leakage current ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I OFF-state output current OZ I power-off leakage current OFF ΔI ...
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... NXP Semiconductors Table 7. Static characteristics At recommended operating conditions; voltages are referenced to GND (ground = 0 V). Symbol Parameter V LOW-level input voltage IL V HIGH-level output voltage OH V LOW-level output voltage OL I input leakage current I I OFF-state output current OZ I power-off leakage current OFF ΔI ...
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... NXP Semiconductors 11. Dynamic characteristics Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation delay see enable time see disable time see dis propagation delay see 74AUP1G240 Product data sheet Figure 9 Min [2] Figure ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions t enable time see disable time see dis propagation delay see enable time see disable time see dis 74AUP1G240 Product data sheet …continued Figure 9 ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions propagation delay see enable time see disable time see dis 74AUP1G240 Product data sheet …continued Figure 9 Min [2] Figure 1 1 ...
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... NXP Semiconductors Table 8. Dynamic characteristics Voltages are referenced to GND (ground = 0 V); for test circuit see Symbol Parameter Conditions pF and power dissipation MHz capacitance [1] All typical values are measured at nominal V [ the same as t and t pd PLH PHL [ the same as t and t ...
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... NXP Semiconductors OE input output LOW-to-OFF OFF-to-LOW output HIGH-to-OFF OFF-to-HIGH Measurement points are given in Logic levels: V and Fig 8. Enable and disable time Table 10. Measurement points Supply voltage Input 0.5 × 1.6 V 0.5 × 2.7 V 0.5 × 3.6 V 74AUP1G240 Product data sheet ...
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... NXP Semiconductors Test data is given in Table Definitions for test circuit Load resistance Load capacitance including jig and probe capacitance Termination resistance should be equal to the output impedance External voltage for measuring switching times. EXT Fig 9. Load circuitry for switching times Table 11. ...
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... NXP Semiconductors 13. Package outline TSSOP5: plastic thin shrink small outline package; 5 leads; body width 1. DIMENSIONS (mm are the original dimensions UNIT max. 0.1 1.0 mm 1.1 0.15 0 0.8 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION IEC SOT353-1 Fig 10 ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 1 x 1. 6× (2) terminal 1 index area DIMENSIONS (mm are the original dimensions) ( UNIT b D max max 0.25 1.5 mm 0.5 0.04 0.17 1.4 Notes 1. Including plating thickness. 2. Can be visible in some manufacturing processes. ...
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... NXP Semiconductors XSON6: plastic extremely thin small outline package; no leads; 6 terminals; body 0 6× (1) terminal 1 index area DIMENSIONS (mm are the original dimensions UNIT b D max max 0.20 1.05 mm 0.5 0.04 0.12 0.95 Note 1. Can be visible in some manufacturing processes. OUTLINE VERSION IEC SOT891 Fig 12 ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 0.9 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 0.95 mm nom 0.15 0.90 min 0.12 0.85 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors XSON6: extremely thin small outline package; no leads; 6 terminals; body 1.0 x 1 (6×) terminal 1 index area Dimensions (1) Unit max 0.35 0.04 0.20 1.05 mm nom 0.15 1.00 min 0.12 0.95 Note 1. Including plating thickness. 2. Visible depending upon used manufacturing technology. ...
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... NXP Semiconductors 14. Abbreviations Table 12. Abbreviations Acronym Description CDM Charged Device Model DUT Device Under Test ESD ElectroStatic Discharge HBM Human Body Model MM Machine Model 15. Revision history Table 13. Revision history Document ID Release date 74AUP1G240 v.2 20100913 • Modifications: Added type number 74AUP1G240GN (SOT1115/XSON6 package). ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. 17. Contact information For more information, please visit: For sales office addresses, please send an email to: 74AUP1G240 Product data sheet Low-power inverting buffer/line driver ...
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... NXP Semiconductors 18. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 5 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 3 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3 7 Functional description . . . . . . . . . . . . . . . . . . . 3 8 Limiting values Recommended operating conditions Static characteristics Dynamic characteristics . . . . . . . . . . . . . . . . . . 8 12 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 13 Package outline ...