DS1077L DALLAS [Dallas Semiconductor], DS1077L Datasheet - Page 16

• Manufacturer Part Number: DS1077L
• Description: 3V EconOscillator/Divider
• Manufacturer: DALLAS [Dallas Semiconductor]

NOTES:
1. All voltages are referenced to ground.
2. 4.87kHz is obtained from a -40MHz standard part.
3. Output voltage swings may be impaired at high frequencies combined with high output loading.
4. After this period, the first clock pulse is generated.
5. A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V
6. The maximum t
7. A fast mode device can be used in a standard mode system, but the requirement t
8. C
9. Jitter accumulates over N clock cycles as: (3 sigma jitter)(no. of cycles)
TIMING DIAGRAM
SDA
ORDERING INFORMATION:
*Future product. Contact factory for availability.
SCL
MIN
SCL signal.
then be met. This will automatically be the case if the device does not stretch the LOW period of the
SCL signal. If such a device does stretch the LOW period of the SCL signal, it must output the next data
bit to the SDA line t
STOP
B
— Total capacitance of one bus line in pF.
t
BUF
of the SCL signal) in order to bridge the undefined region of the falling edge of SCL.
START
DS1077L
t
HD:STA
t
LOW
HD
:
DAT
R MAX
PACKAGE TYPE:
Z = SO (150MIL)
U = µSOP*
t
R
t
HD:DAT
has only to be met if the device does not stretch the low period (t
+ t
SU
:
DAT
t
HIGH
= 1000 + 250 = 1250ns before the SCL line is released.
t
F
t
SU:DAT
16 of 20
t
SU:STA
REPEATED
Master Frequency (MHz)
40, 50, 60, 66.66
START
t
HD:STA
0.65
.
SU
t
SP
:
DAT
t
SU:STO
>250ns must
LOW
) of the
IH