DS1077L DALLAS [Dallas Semiconductor], DS1077L Datasheet
DS1077L
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DS1077L Summary of contents
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... Preprogrammed devices can be ordered in customer-requested frequencies. The DS1077L is available µSOP packages, allowing the generation of a clock signal easily, economically, and using minimal board area. Chip-scale packaging is also available on request. ...
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... BLOCK DIAGRAM DS1077L Figure 1 INTERNAL OSCILLATOR DIV1 0M1 0M0 1M1 1M0 EN0 SEL0 PDN0 PDN1 CONTROL REGISTERS 2-WIRE INTERFACE SDA SCL MCLK MUX P0 PRESCALER (M DIVIDER) 0M1 0M0 P1 PRESCALER (M DIVIDER) Power-Down 1M1 1M0 PDN1 CONTROL SEL0 LOGIC EN0 (TABLE 1) PDN 0 Enable ...
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... OVERVIEW A block diagram of the DS1077L is shown in Figure 1. The DS1077L consists of four major components: 1) internal master oscillator, 2) prescalers, 3) programmable divider, and 4) control registers. The internal oscillator is factory trimmed to provide a master frequency (master clk) that can be routed directly to the outputs (OUT0 & OUT1) or through separate prescalers (P0 & P1). OUT1 can also be routed through an additional divider (N) ...
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TABLE 1 EN0 SEL0 PDN0 (BIT) (BIT) (BIT *This mode is for applications where OUT0 is not used, but CTRL0 is used ...
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TABLE 3 PDN0 PDN1 (BIT) (BIT *CTRL0 performs a power-down if SEL0 and EN0 are both 0. (See Table 1.) Serial Data Input/Output (SDA) – Input/output pin for the 2-wire serial interface ...
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EN0 (bit) If EN0 = 1 and PDN0 = 0, the CTRL0 pin functions as an output enable for OUT0, the frequency of the output is determined by the SEL0 bit. If PDN0 = 1, the EN0 bit is ignored, ...
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... START and STOP conditions. The DS1077L operates as a slave on the 2-wire bus. Connections to the bus are made via the open-drain I/O lines, SDA and SCL. A pullup resistor (5k) is connected to SDA ...
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... When the DS1077L EEPROM is being written to, it will not be able to perform additional responses. In this case, the slave DS1077L will send a ‘not acknowledge’ to any data transfer request made by the master. It will resume normal operation when the EEPROM operation is complete ...
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... A control byte is the first byte received following the START condition from the master device. The control byte consists of a four-bit control code; for the DS1077L, this is set as 1011 binary for read and write operations. The next three bits of the control byte are the device select bits (A2, A1, and A0) and can be written to the EEPROM ...
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... SERIAL COMMUNICATION WITH DS1077L Figure 3 Send a “Standalone” Command SCL SDA Start Address Byte DS1077L Write MSB of a Two-Byte Register SCL SDA Start Address Byte DS1077L ACK Write to a Two-Byte Register ...
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... SERIAL COMMUNICATION WITH DS1077L Figure 3 (cont.) Read Single Byte Register or MSB from a Two-Byte Register SCL SDA Start Control Byte DS1077L ACK Read from a Two-Byte Register SCL SDA Start Control Byte ...
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... COMMAND SET Data and control information is read from and written to the DS1077L in the format shown in Figure 3. To write to the DS1077L, the master will issue the slave address of the DS1077L and the R/ 0. After receiving an acknowledge, the bus master provides a command protocol. After receiving this protocol, the DS1077L will issue an acknowledge, and then the master can send data to the DS1077L ...
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... SDA and SCL V IL CTRL0 and CTRL1 3. 3.6V 15pF L (both outputs) I Power-Down CCQ Mode 2.7V to 3.6V) CC MIN TYP MAX UNITS 2.7 3.6 V 2.4 V 0 0.3 CC 1.4 0. 0.3 CC 0.6 1 µA -1 µ µA DS1077L NOTES 1 ...
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AC ELECTRICAL CHARACTERISTICS PARAMETER Output Frequency Tolerance (from Nominal) Combined Freq. Variation (from Nominal) Output Frequency Min Output Frequency Max Power-Up Time Enable OUT1 from CTRL1 Enable OUT0 from CTRL0 OUT1 Hi-Z from CTRL1 OUT0 Hi-Z from CTRL0 Load Capacitance ...
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AC ELECTRICAL CHARACTERISTICS: 2-WIRE INTERFACE PARAMETER SYMBOL SCL Clock Frequency Bus Free Time Between a STOP and START Condition Hold Time (Repeated) START Condition. LOW Period of SCL HIGH Period of SCL Setup Time for a Repeated START Data Hold ...
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... Jitter accumulates over N clock cycles as: (3 sigma jitter)(no. of cycles) TIMING DIAGRAM SDA t BUF t t LOW R SCL t HD:STA t HD:DAT STOP START ORDERING INFORMATION: DS1077L PACKAGE TYPE (150MIL µSOP* *Future product. Contact factory for availability 1000 + 250 = 1250ns before the SCL line is released DAT HIGH SU:STA ...
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TYPICAL OPERATING CHARACTERISTICS 2 3.3V SUPPLY CURRENT vs. TEMPERATURE TEMPERATURE (C) SUPPLY ...
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TYPICAL OPERATING CHARACTERISTICS (cont.) 3.4 3.2 3 2.8 2.6 2.4 2 4.5 4 3 3.3V +25ºC, unless otherwise specified SUPPLY CURRENT vs. DIVISOR (FREQUENCY) 100 200 300 400 ...
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... TYPICAL OPERATING CHARACTERISTICS (cont.) 0.880 0.860 0.840 0.820 0.800 0.780 0.760 0 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0 3.3V +25ºC, unless otherwise specified DS1077L SHUTDOWN CURRENT vs. TEMPERATURE TEMPERATURE (C) DS1077L TEMPCO TEMPERATURE ( 66MHz device -66 device -60 device -50 device -40 device ...
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... TYPICAL OPERATING CHARACTERISTICS (cont.) 1 0.8 0.6 0.4 0.2 0 -0.2 -0.4 -0.6 -0 3.3V +25ºC, unless otherwise specified DS1077L VOLTCO 2.8 2.9 3.0 3.1 SUPPLY VOLTAGE ( -66 device -60 device -50 device -40 device 3.2 3.3 3.4 3.5 3.6 ...