DS1023-025 DALLAS [Dallas Semiconductor], DS1023-025 Datasheet
DS1023-025
Related parts for DS1023-025
DS1023-025 Summary of contents
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... DIP or SOIC package DESCRIPTION The DS1023 is an 8-bit programmable delay line similar in function to the DS1020/DS1021. Additional features have been added to extend the range of applications: The internal delay line architecture has been revised to allow clock signals to be delayed full period or more. Combined with an on-chip reference delay (to offset the inherent or “ ...
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... SERIAL MODE ( / the SERIAL programming mode, the output of the DS1023 will reproduce the logic state of the input after a delay time determined by an 8-bit value clocked into serial port D. While observing data setup (t ) and data hold (t ...
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... Applications can read the setting of the DS1023 Delay Line by connecting the serial output pin (Q) to the serial input (D) through a resistor with a value kohms (Figure 2). Since the read process is destructive, the resistor restores the value read and provides isolation when writing to the device. The resistor must connect the serial output (Q) of the last device to the serial input (D) of the first device of a daisy chain (Figure 1) ...
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... INPUT PULSE DURATION The internal architecture of the DS1023 allows the output delay time to be considerably longer than the input pulse width (see ac specifications). This feature is useful in many applications, in particular clock phase control where delays up to and beyond one full clock period can be achieved. ...
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... A programmed value of zero will still result in a non-zero delay as indicated in the Step Zero delay specification. The free-running oscillator. The frequency of oscillation is determined by the programmed delay value of the device (see Table 2). Name Pin Number PWM 9 15 OUT pin may also be externally connected to the input pin to produce a OUT DS1023 ...
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... FUNCTIONAL BLOCK DIAGRAM Figure 5 DELAY LINE DETAIL (CONCEPTUAL) - DS1023-200, DS1023-500 Figure DS1023 ...
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... This is the deviation from a straight line drawn between the step zero value and the maximum programmed delay time. OSCILLATOR CONFIGURATION Table 2 PART NUMBER DS1023-025 DS1023-050 DS1023-100 DS1023-200 DS1023-500 4 ...
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... The input waveform is produced by a precision pulse generator under software control. Time delays are measured by a time interval counter (20 ps resolution) connected to the output. The DS1023 serial and parallel ports are controlled by interfaces to a central computer. All measurements are fully automated with each instrument controlled by the computer over an IEEE 488 bus ...
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... (0°C to 70° ± 5%) CC MAX UNITS µ 5 MAX UNITS 10 MHz 500 ns ns 500 ns ns 100 ms DS1023 NOTES NOTES ...
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... TIMING DIAGRAM: SILICON DELAY LINE Figure 9 AC ELECTRICAL CHARACTERISTICS - DS1023-025 Delay Specifications PARAMETER Step Zero Delay -absolute -wrt REF Reference Delay Delay Step Size Maximum Delay -absolute -wrt REF Delay Matching, Rising Edge to Falling Edge Integral Non-linearity (deviation from straight line) ...
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... AC ELECTRICAL CHARACTERISTICS – DS1023-050 Delay Specifications PARAMETER Step Zero Delay -absolute -wrt REF Reference Delay Delay Step Size Maximum Delay -absolute -wrt REF Delay Matching, Rising Edge to Falling Edge Integral Non-linearity (deviation from straight line) Delta Delay OUT IN High to PWM High ...
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... AC ELECTRICAL CHARACTERISTICS - DS1023-200 Delay Specifications PARAMETER Step Zero Delay -absolute -wrt REF Reference Delay Delay Step Size Maximum Delay -absolute -wrt REF Delay Matching, Rising Edge to Falling Edge Integral Non- linearity (deviation from straight line) Delta Delay OUT IN High to PWM High ...
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... This is the difference in measured delay between rising edge (input to output), t (input to output 16. Faster rise and fall times will give the greatest accuracy in measured delay. Slow edges (outside the specification maximum) may result in erratic operations. . (See Figure 15 DS1023 This parameter and falling edges DR ...
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... Delay): The elapsed time between the 1.5V point on the edge of an input pulse and the 1.5V D point on the corresponding edge of the output pulse. TIMING DIAGRAM: NON-LATCHED PARALLEL MODE ( / Figure 10 P TIMING DIAGRAM: LATCHED PARALLEL MODE ( / Figure DS1023 ...
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... TIMING DIAGRAM: SERIAL MODE ( DELAY vs PROGRAMMED VALUE Figure 13 t DMAX (measured Figure DS1023 ...
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... DO 3. Consequently the range of absolute delay values (t amount equal DREF0 = 255 * (nominal step size). DREF , the actual step size will be slightly above the nominal value. REF -t ) will also exceed the nominal range by an DMAX DS1023 ...