ov9650 OmniVision Technologies, Inc, ov9650 Datasheet

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ov9650

Manufacturer Part Number
ov9650
Description
Color Cmos Sxga 1.3 Megapixel Camerachiptm With Omnipixel
Manufacturer
OmniVision Technologies, Inc
Datasheet

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OV9650
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Agilent
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ov9650-AGEL
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OV9650 Color CMOS SXGA (1.3 MegaPixel) C
General Description
Features
Ordering Information
Version 1.91, January 28, 2005
The OV9650 C
image sensors that provides the full functionality of a
single-chip SXGA (1280x1024) camera and image
processor in a small footprint package. The OV9650
provides full-frame, sub-sampled or windowed 8-bit/10-bit
images in a wide range of formats, controlled through the
Serial Camera Control Bus (SCCB) interface.
This product has an image array capable of operating at
up to 15 frames per second (fps) in SXGA resolution with
complete user control over image quality, formatting and
output data transfer. All required image processing
functions, including exposure control, gamma, white
balance, color saturation, hue control, white pixel
canceling,
programmable through the SCCB interface. In addition,
OmniVision
technology to improve image quality by reducing or
eliminating common lighting/electrical sources of image
contamination, such as fixed pattern noise, smearing,
etc., to produce a clean, fully stable color image.
OV09650-KL1A (Color)
High sensitivity for low-light operation
Low operating voltage for embedded portable
Standard SCCB interface
Supports SXGA, VGA, QVGA, QQVGA, CIF, QCIF,
Automatic image control functions including:
Image quality controls including color saturation,
applications
QQCIF, and windowed outputs with Raw RGB, RGB
(GRB 4:2:2), YUV (4:2:2) and YCbCr (4:2:2) formats
(VGA, QVGA, QQVGA, CIF, QCIF, and QQCIF)
Automatic Exposure Control (AEC), Automatic Gain
Control (AGC), Automatic White Balance (AWB), and
Automatic Black-Level Calibration (ABLC)
hue, gamma, sharpness (edge enhancement), lens
correction, white pixel canceling, and noise canceling
VarioPixel
Product
noise
C
TM
AMERA
AMERA
method for sub-sampling formats
canceling,
C
C
HIPS
HIP
TM
use
is a low voltage CMOS
and
proprietary
Package
CSP-28
more,
TM
are
sensor
also
AMERA
Proprietary to OmniVision Technologies
Applications
Key Specifications
Figure 1 OV9650 Pin Diagram
Requirements
Power Supply
Transfer Rate
Temperature
Maximum
C
Maximum Exposure Interval 1050 x t
Cellular and Picture Phones
Toys
PC Multimedia
Digital Still Cameras
Power
Range
HIP TM
Image
Output Formats (8-bit)
Package Dimensions 5095 µm x 5715 µm
Fixed Pattern Noise <0.03% of V
QVGA, QQVGA, CIF 60 fps
Gamma Correction Programmable
PWDN
VREF
HREF
PCLK
with OmniPixel
A1
B1
C1
D0
D1
D1
E1
F1
Active Array Size 1300 x 1028
Dynamic Range 62 dB
Well Capacity 28 K e
Stable Image 0°C to 50°C
Dark Current 30 mV/s at 60°C
Preliminary Datasheet
XVCLK1
QCIF, QQCIF 120 fps
VSYNC
DOVDD
Advanced Information
AVDD
NVDD
DVDD
Image Area 4.13 mm x 3.28 mm
Scan Mode Progressive
A2
B2
C2
D2
E2
F2
Sensitivity 0.9 v/Lux-sec
Operation -20°C to 70°C
Lens Size 1/4"
Pixel Size 3.18 µm x 3.18 µm
S/N Ratio 40 dB
Standby 30 µW
Analog 2.45 to 2.8 VDC
OV9650
Active
SXGA 15 fps
DOGND
RESET
SIO_D
AGND
Core 1.8VDC + 10%
VGA 30 fps
A3
B3
E3
F3
I/O 2.5V to (V
50 mW (15 fps, no I/O
power)
• YUV/YCbCr 4:2:2
• GRB 4:2:2
• Raw RGB Data
SIO_C
A4
B4
C4
NC
D4
NC
D2
E4
D8
F4
D9
TM
Technology
ROW
NC
A5
D4
B5
D3
C5
D5
D5
E5
D6
D7
F5
DD-A
PEAK-TO-PEAK
+0.3V)
1

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ov9650 Summary of contents

Page 1

... HIP image sensors that provides the full functionality of a single-chip SXGA (1280x1024) camera and image processor in a small footprint package. The OV9650 provides full-frame, sub-sampled or windowed 8-bit/10-bit images in a wide range of formats, controlled through the Serial Camera Control Bus (SCCB) interface. ...

Page 2

... Functional Description Figure 2 shows the functional block diagram of the OV9650 image sensor. The OV9650 includes: • Image Sensor Array (1300 x 1028 active image array) • Analog Signal Processor • A/D Converters • Digital Signal Processor (DSP) • Output Formatter • Timing Generator • ...

Page 3

... O mni ision Image Sensor Array The OV9650 sensor has an active image array of 1300 columns by 1028 rows (1,336,400 pixels). a cross-section of the image sensor array. Figure 3 Image Sensor Array Microlens Green Blue Timing Generator In general, the timing generator controls the following functions: • ...

Page 4

Pin Description Table 1 Pin Description Pin Location Name Pin Type Function A1 PWDN (default = 0) A2 AVDD Power A3 SIO_D A4 D2 Output A5 D4 Output B1 VREF V B2 NVDD V B3 AGND Power B4 SIO_C Input ...

Page 5

O mni ision Electrical Characteristics Table 2 Absolute Maximum Ratings Ambient Storage Temperature Supply Voltages (with respect to Ground) All Input/Output Voltages (with respect to Ground) Lead-free Temperature, Surface-mount process ESD Rating, Human Body model NOTE: Exceeding the Absolute Maximum ...

Page 6

Table 4 Functional and AC Characteristics (-20°C < T Symbol Functional Characteristics A/D Differential Non-Linearity A/D Integral Non-Linearity AGC Range Red/Blue Adjustment Range Inputs (PWDN, CLK, RESET) Input Clock Frequency f CLK Input Clock Period t CLK Clock Duty Cycle ...

Page 7

O mni ision Timing Specifications Figure 4 SCCB Timing Diagram t F SIO_C t SU:STA SIO_D IN SIO_D OUT Figure 5 Horizontal Timing PCLK HREF D[9:0] Last Byte Figure 6 SXGA Frame Timing VSYNC LINE HREF 16 ...

Page 8

Figure 7 VGA Frame Timing VSYNC LINE HREF HSYNC D[9:0] Invalid Data NOTE: For Raw data internal pixel clock P For YUV/RGB internal pixel clock P Figure 8 ...

Page 9

O mni ision Figure 10 CIF Frame Timing VSYNC LINE HREF HSYNC D[9:0] Invalid Data NOTE: For Raw data internal pixel clock P For YUV/RGB internal pixel clock ...

Page 10

Figure 13 RGB 565 Output Timing Diagram PCLK HREF Last Byte D[9:2] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] Figure 14 RGB 555 Output Timing Diagram PCLK HREF Last Byte D[9:2] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] ...

Page 11

... O mni ision OV9650 Light Response Figure 15 OV9650 Light Response Version 1.91, January 28, 2005 Proprietary to OmniVision Technologies Timing Specifications 11 ...

Page 12

... Register Set Table 5 provides a list and description of the Device Control registers contained in the OV9650. For all register Enable/Disable bits, ENABLE = 1 and DISABLE = 0. The device slave addresses are 60 for write and 61 for read. Table 5 Device Control Register List Address Register Default (Hex) ...

Page 13

O mni ision Table 5 Device Control Register List (Continued) Address Register Default (Hex) Name (Hex) 09 COM2 01 0A PID 96 0B VER 52 0C COM3 00 0D COM4 00 0E COM5 01 Version 1.91, January 28, 2005 R/W ...

Page 14

Table 5 Device Control Register List (Continued) Address Register Default (Hex) Name (Hex) 0F COM6 43 10 AECH 40 11 CLKRC 00 12 COM7 00 13 COM8 8F 14 Proprietary to OmniVision Technologies AMERA R/W Common Control 6 Bit[7]: Output ...

Page 15

O mni ision Table 5 Device Control Register List (Continued) Address Register Default (Hex) Name (Hex) 14 COM9 4A 15 COM10 00 16 RSVD 00 17 HSTART 1A 18 HSTOP BA 19 VSTRT 01 1A VSTOP 81 1B PSHFT 00 ...

Page 16

Table 5 Device Control Register List (Continued) Address Register Default (Hex) Name (Hex) 1D MIDL A2 1E MVFP 00 1F LAEC 00 20 BOS 80 21 GBOS 80 22 GROS 80 23 ROS 80 24 AEW 78 25 AEB 68 ...

Page 17

O mni ision Table 5 Device Control Register List (Continued) Address Register Default (Hex) Name (Hex) 28 GbBIAS 80 29 Gr_COM 00 2A EXHCH 00 2B EXHCL 00 2C RBIAS 80 2D ADVFL 00 2E ADVFH 00 2F YAVE 00 ...

Page 18

Table 5 Device Control Register List (Continued) Address Register Default (Hex) Name (Hex) 3A TSLB 0C 3B COM11 00 3C COM12 40 18 Proprietary to OmniVision Technologies AMERA R/W Line Buffer Test Option Bit[7:6]: Reserved Bit[5]: Bit-wise reverse Bit[4]: UV ...

Page 19

O mni ision Table 5 Device Control Register List (Continued) Address Register Default (Hex) Name (Hex) 3D COM13 99 3E COM14 0E 3F EDGE 88 40 COM15 C0 41 COM16 10 42 COM17 08 Version 1.91, January 28, 2005 R/W ...

Page 20

Table 5 Device Control Register List (Continued) Address Register Default (Hex) Name (Hex) 43-4E RSVD XX 4F MTX1 58 50 MTX2 48 51 MTX3 10 52 MTX4 28 53 MTX5 48 54 MTX6 70 55 MTX7 40 56 MTX8 40 ...

Page 21

O mni ision Table 5 Device Control Register List (Continued) Address Register Default (Hex) Name (Hex) 8C COM22 00 8D COM23 00 8E COM24 00 8F DBLC1 0F 90 DBLC_B 00 91 DBLC_R 00 92 DM_LNL 00 93 DM_LNH 00 ...

Page 22

Table 5 Device Control Register List (Continued) Address Register Default (Hex) Name (Hex) A1 AECHM 40 A2-A3 RSVD XX A4 COM25 00 A5 COM26 00 A6 G_GAIN 80 A7 VGA_ST 14 A8-AA ACOM XX NOTE: All other registers are factory-reserved. ...

Page 23

... O mni ision Package Specifications The OV9650 uses a 28-pin Chip Scale Package (CSP). Refer to dimensions and Figure 17 for the array center on the chip. Note: For OVT devices that contain lead, all part marking letters are upper case. For OVT devices that are lead-free, all part marking letters ...

Page 24

... NOTES: 1. This drawing is not to scale and is for reference only most optical assemblies invert and mirror the image, the chip is typically mounted with pins oriented down on the PCB. The recommended lens chief ray angle for the OV9650 is 20 degrees. 24 Proprietary to OmniVision Technologies ...

Page 25

... Peak Temperature Cool-down Rate (Peak to 50°C) Time from 30°C to 255°C Environmental Specifications Table 8 OV9650 Reliability Test Results Parameter Temperature/Humidity Temperature Cycling (Air-to-Air) Highly Accelerated Stress Test (HAST) High Temperature Storage (HTS) High Temperature Static Bias (HTSB) a. Pre-Condition (Moisture Level II): 125° ...

Page 26

... OmniVision web site (http://www.ovt.com) to obtain the current versions of all documentation. • OmniVision Technologies, Inc. reserves the right to make changes to their products or to discontinue any product or service without further notice (It is advisable to obtain current product documentation prior to placing orders). • ...

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