UPD16488AP NEC [NEC], UPD16488AP Datasheet - Page 10

• Manufacturer Part Number: UPD16488AP
• Description: 1/92 DUTY LCD CONTROLLER/DRIVER WITH FOUR-LEVEL GRAY SCALE, ON-CHIP RAM
• Manufacturer: NEC [NEC]

3.2
PSX
/CS1,
CS2
/RD
(E)
/WR
(R,/W)
C86
D
D
D
RS
/RES
0
6
7
Symbol
10
to D
(SCL)
(SI)
Logic System Pins
5
,
Data transfer
selection
Chip select
Read
(enable)
Write
Interface selection
Data bus
(serial clock)
(serial input)
Index
register/data,
command
selection
Reset
(read/write)
Name
105 to 108, 110 to 113,
115 to 118,
120 to 123
102, 103
100, 101
Pad No.
90, 91,
84, 85
92, 93
82, 83
97, 98
95, 96
Data Sheet S15745EJ2V0DS
Input
Input
Input
Input
Input
Input
Input
I/O
I/O
This pin is used to select between parallel data input and serial
data input.
PSX = H: Parallel data input
PSX = L: Serial data input
These pins are used for chip select signals. When /CS1 = L
(CS2 = H), the chip is active and can perform data input/output
operations including command and data I/O.
When i80 series parallel data transfer (/RD) has been selected,
the signal at this pin is used to enable read operations. Data is
output to the data bus only when this pin is L.
When M68 series parallel data transfer (E) has been selected,
the signal at this pin is used to enable write operations. Data is
written at the falling edge of this signal.
When i80 series parallel data transfer (/WR) has been selected,
the signal at this pin is used to enable write operations. Data is
written at the rising edge of this signal.
When 68 series parallel data transfer (R,/W) has been selected,
this pin is used to determine the direction of data transfer.
L: Write
H: Read
This pin is used to switch between interface modes (i80 series
CPU or M68 series CPU).
L: Selects i80 series CPU mode
H: Selects M68 series CPU mode
These pins comprise an 8-bit bidirectional data bus that
connects to an 8-bit or 16-bit standard CPU bus.
When the serial interface has been selected (PSX = L), D
functions as a serial clock input pin (SCL) and D
serial data input pin (SI). In either case, pins D
high impedance mode.
When the chip is not selected, D
mode.
Usually, this pin is connected to the LSB of the standard CPU
address bus and is used to distinguish between data from index
registers and data/commands.
RS = H: Indicates that data from D
RS = L : Indicates that data from D
When /RES is low, an internal reset is performed. The reset
operation is executed at the /RES signal level.
contents
Description
0
to D
0
0
to D
to D
7
are in high impedance
7
7
is data/command
is index register
0
7
to D
functions as a
µ µ µ µ PD16488A
5
are in
6
(1/3)