ch7003b-v Chrontel, ch7003b-v Datasheet - Page 24

• Manufacturer Part Number: ch7003b-v
• Description: Ch7003 Digital Pc To Tv Encoder
• Manufacturer: Chrontel

CHRONTEL
4.6 Serial Port Operation
The CH7003 contains a standard serial control port, through which the control registers can be written and read.
This port is comprised of a two-wire serial interface, pins SD (bi-directional) and SC, which can be connected
directly to the SDB and SCB buses as shown in Figure 19.
The Serial Clock line (SC) is input only and is driven by the output buffer of the master device (also shown in
Figure 19). The CH7003 acts as a slave, and generation of clock signals on the bus is always the responsibility of
the master device. When the bus is free, both lines are HIGH. The output stages of devices connected to the bus
must have an open-drain or open-collector to perform the wired-AND function. Data on the bus can be transferred
up to 400 kbit/s.
Electrical Characteristics for Bus Devices
The electrical specifications of the bus devices’ inputs and outputs and the characteristics of the bus lines connected
to them are shown in Figure 19. A pull-up resistor (R
a device with input levels related to V
Maximum and minimum values of pull-up resistor (R
The value of R
The supply voltage limits the minimum value of resistor R
VOL
The bus capacitance is the total capacitance of wire, connections and pins. This capacitance limits the maximum
value of R
The maximum HIGH level input current of each input/output connection has a specified maximum value of 10 A.
Due to the desired noise margin of 0.2V
The R
24
max
• Supply voltage
• Bus capacitance
• Number of devices connected (input current + leakage current = I
P
limit depends on V
SDB (Serial Data Bus)
SCB (Serial Clock Bus)
= 0.4 V for the output stages:
SCLK
OUT
FROM
MASTER
P
due to the specified rise time. The equation for RP is shown below:
P
depends on the following parameters:
BUS MASTER
R
R
R
DATA IN
MASTER
DATAN2
OUT
MASTER
P
P
P
>= (V
<= 10
<= (100 x V
DD
Figure 19: Connection of Devices to the Bus
and is shown below:
3
DD
/C (where: R
– 0.4) / 3 (R
DD
DD
)/ I
DD
.
SCLK
IN1
input
for the HIGH level, this input current limits the maximum value of R
P
is in k and C, the total capacitance, is in pF)
P
(where: R
in k
SLAVE
SC
P
DATAN2
OUT
) must be connected to a 5V ± 10% supply. The CH7003 is
DATA
IN1
P
P
is in k and I
due to the specified minimum sink current of 3mA at
P
)
SD
R
P
input
input
SCLK
IN2
)
is in A)
201-0000-023 Rev. 4.2, 4/12/2002
SLAVE
+VDD
DATAN2
OUT
DATA
IN2
CH7003B
P
.