ch7009a ETC-unknow, ch7009a Datasheet - Page 40

• Manufacturer Part Number: ch7009a
• Description: Chrontel Ch7009 Dvi / Tv Output Device
• Manufacturer: ETC-unknow

CHRONTEL
DVI PLL Filter Register
Bits 3-0 of register TPT are reserved bits, and should be left at the default value.
Bits 7-4 of register TPT control the DVI PLL low pass filter. The default value is recommended.
DVI PLL VCO Control Overflow Register
Bits 4-0 of register TCT are reserved bits, and should be left at the default value.
Bits 7-5 of register TCT contain the MSB values for the DVI PLL VCO control. This control is described in detail
in the TVCO register description.
Test Pattern Register
Bits 1-0 of register TSTP control the test pattern generation block. This test pattern can be used for both the DVI
output and the TV Output. The pattern generated is determined by Table 22 below.
Table 22: Test Pattern Control
40
DEFAULT:
DEFAULT:
DEFAULT:
TSTP[1:0]
00
01
1X
SYMBOL:
SYMBOL:
SYMBOL:
TYPE:
TYPE:
TYPE:
BIT:
BIT:
BIT:
TPVCO10
Buffered Clock Output
No test pattern – Input data is used
Color Bars
Horizontal Luminance Ramp
TPLPF3
R/W
R/W
7
0
7
0
7
TPVCO9 TPVCO8 Reserved Reserved Reserved Reserved
TPLPF2
R/W
R/W
6
6
0
6
0
TPLPF1
R/W
R/W
5
5
0
5
0
TPLPF0 Reserved Reserved Reserved
ResetIB ResetDB
R/W
R/W
R/W
4
1
4
0
4
0
R/W
R/W
R/W
3
1
3
0
3
0
RSA
R/W
R/W
R/W
201-0000-035 Rev 1.1, 5/8/2000
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
2
0
2
0
2
0
TSTP1
R/W
R/W
R/W
CH7009A
1
0
1
0
1
0
TPF
36h
8
TVCOO
37h
8
TSTP
48h
5
Reserved
Reserved
TSTP0
R/W
R/W
R/W
0
0
0
0
0
0