ch7009a ETC-unknow, ch7009a Datasheet - Page 38

• Manufacturer Part Number: ch7009a
• Description: Chrontel Ch7009 Dvi / Tv Output Device
• Manufacturer: ETC-unknow

CHRONTEL
Buffered Clock Output Register
Bits 2-0 of register BCO select the signal output at the BCO pin, according to Table 20 below:
Table 20: BCO Output Signal
Bit 3 of register BCO selects the polarity of the BCO output. A value of ‘1’ does not invert the signal at the output
pad.
Bit 4 of register BCO enables the BCO output. When BCOEN is high, the BCO pin will output the selected signal.
When BCOEN is low, the BCO pin will be held in tri-state mode.
Bits 7-5 of register BCO select the K3 divider, according to Table 21 below.
Table 21: K3 Selection
DVI Control Input Register
Bits 3-0 of register TCTL set the DVI control inputs applied to the green and red channels during sync intervals. It
is recommended to leave these controls at the default value.
Bits 7-4 of register TCTL control the DVI PLL phase detector. The default value is recommended.
38
DEFAULT:
DEFAULT:
BCO[2:0]
000
001
010
011
SHF[2:0]
000
001
010
011
100
101
110
111
SYMBOL:
SYMBOL:
TYPE:
TYPE:
BIT:
BIT:
Buffered Clock Output
The 14MHz crystal
(for test use only)
VCO divided by K3
Field ID
K3
2.5
3.0
3.5
4.0
4.5
5.0
6.0
7.0
TPPD3
SHF2
R/W
R/W
7
1
7
0
TPPD 2
SHF1
R/W
R/W
6
0
6
0
TPPD 1
SHF0
R/W
R/W
5
0
5
0
BCOEN
TPPD 0
BCO[2:0]
100
101
110
111
R/W
R/W
4
0
4
0
BCOP
CTL3
R/W
R/W
Buffered Clock Output
(for test use only)
(for test use only)
VGA Vertical Sync
TV Vertical Sync
3
0
3
0
BCO2
CTL2
R/W
R/W
201-0000-035 Rev 1.1, 5/8/2000
Symbol:
Address:
Bits:
Symbol:
Address:
Bits:
2
0
2
0
BCO1
CTL1
R/W
R/W
CH7009A
1
0
1
0
BCO
22h
8
TCTL
31h
8
BCO0
CTL0
R/W
R/W
0
0
0
0