sh6631a SinoWealth Micro-Electronics Corp. Ltd, sh6631a Datasheet - Page 11

• Manufacturer Part Number: sh6631a
• Description: Mask 4-bit Microcontroller
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

8. Interrupt
Two interrupt sources are available on SH6631A:
Interrupt Control Bits and Interrupt Service
The interrupt control flags are mapped on $00 through $01 of the system register. They can be accessed or tested by the
program. These flags are cleared to 0 at initialization by chip reset.
When IEx is set to 1 and the interrupt request is generated (IRQx is 1) , the interrupt will be activated and vector address will be
generated from the priority PLA corresponding to the interrupt sources. When an interrupt occurs, the PC and CY flag will be
saved into stack memory and jump to interrupt service vector address. After the interrupt occurs, all interrupt enable flags (IEx)
are reset to 0 automatically, thus, when IRQx is 1 and IEx is set to 1 again, the interrupt will be activated and vector address will
be generated from the priority PLA corresponding to the interrupt sources.
Interrupt Servicing Sequence Diagram:
Interrupt Nesting:
During the SH6610C CPU interrupt service, the user can enable any interrupt enable flag before returning from the interrupt.
The servicing sequence diagram shows the next interrupt and the next nesting interrupt occurrences. If the interrupt request is
ready and the instruction of execution N is IE enable, then the interrupt will start immediately after the next two instruction
executions. However, if instruction I1 or instruction I2 disables the interrupt request or enable flag, then the interrupt service will
be terminated.
9. HALT and STOP mode
After the execution of HALT instruction, SH6631A will enter HALT mode. In HALT mode, the CPU will stop operating; however,
the peripheral circuit (timer) will keep operating.
After the execution of STOP instruction, SH6631A will enter STOP mode.
In STOP mode, the entire chip (including oscillator) will stop operating.
In HALT mode, SH6631A can be woken up if an interrupt occurs.
In STOP mode, SH6631A can be woken up if a port interrupt occurs.
10. Warm-up Timer
The SH6631A has a built in oscillator warm-up timer to eliminate unstable state of initial oscillation when oscillator starts
oscillating in the following conditions:
(1) Power-on reset
(2) Wake-up from STOP mode
The warm-up time interval (F
(1) Power-on reset interval is as long as the initial oscillator’s frequency mode warm-up timer interval.
(2) 4MHz crystal oscillator wake-up:
When SH6631A operates in 455K Hz frequency, the warm-up time interval is 1.13 ms.
When SH6631A operates in 4 MHz frequency, the warm-up time interval is 0.128 ms.
-Timer0 overflow interrupt
-Port's falling edge detection interrupt ( PBC )
Inst. cycle
Address
$00
$01
Interrupt Generated
Instruction
OSC
Execution
Bit3
N
1
/512 cycles of oscillator) is a follows:
-
-
IRQT0
IET0
Bit2
Interrupt Accepted
Instruction
Execution
I1
2
Bit1
-
-
11
Vector Generated
Instruction
Execution
IRQP
Bit0
IEP
Stacking
I2
3
interrupt enable flags
interrupt request flags
Fetch Vector address
Reset IE.X
Remarks
4
Start at vector
address
5
SH6631A