sh66l16a SinoWealth Micro-Electronics Corp. Ltd, sh66l16a Datasheet - Page 25

• Manufacturer Part Number: sh66l16a
• Description: 16k 4-bit Low Power Micro-controller With Lcd Driver
• Manufacturer: SinoWealth Micro-Electronics Corp. Ltd

12. Read ROM Data Table (RDT)
System Register:
The RDT register consists of a 14 bit write-only PC address load register (RDT.13 - RDT.0) and a 16-bit read-only ROM table
data read-out register (RDT.15 - RDT.0).
To read out the ROM table data, users should fill 0 to higher 2 bit (Bit 14 - 15), write the ROM table address to RDT register (high
nibble first then low nibble), after one instruction, the right data will put into RDT register automatically (write lowest nibble of
address into register will start the data read-out action).
13. HALT and STOP
After the execution of HALT instruction, SH66L16A will enter the HALT mode. In the HALT mode, the CPU will stop operating.
But peripheral circuit (Timer0, Base Timer, LCD driver…) will keep status.
After the execution of STOP instruction, SH66L16A will enter the STOP mode. The whole chip (including oscillator) will stop
operating. But the peripheral circuits such as the OSC oscillator, the LCD driver and the Base Timer can keep status if these
function blocks have been enabled before entering the STOP mode with the “ System Clock selection” code option being equal
to CK = 0,0 or CK = 0,1 .
In the HALT mode, SH66L16A can be waked up if any interrupt occurs.
In the STOP mode, SH66L16A can be waked up if port interrupt occurs. SH66L16A can also be waked up by the Base Timer
interrupt if the OSC oscillator and the Base Timer have been enabled before entering the STOP mode with the “ System Clock
selection” code option being equal to CK = 0,0 or CK = 0,1 .
When CPU is awaked from the HALT/STOP by any interrupt source, it will execute the relevant interrupt serve subroutine at
first. Then the instruction next to HALT/STOP is executed.
14. Warm-up Timer
The device has a built-in warm-up timer to eliminate unstable state of initial oscillation when oscillator starts oscillating in the
following conditions:
14.1. If the “ Single Solar Supply Application selection” code option is equal to “ Enable ”, the warm-up timer interval is defined
as below.
Power-on Reset for OSCX or OSC
In 200kHz RC oscillator mode, the warm-up counter prescaler divide ratio is 1/2
In 32.768kHz Crystal oscillator mode, the warm-up counter prescaler divide ratio is 1/2
Pin Reset for OSCX or OSC
In 200kHz RC oscillator mode, the warm-up counter prescaler divide ratio is 1/2
In 32.768kHz Crystal oscillator mode, the warm-up counter prescaler divide ratio is 1/2
Register control on for OSC
In 32kHz RC oscillator mode, the warm-up counter prescaler divide ratio is 1/2
In 32.768kHz Crystal oscillator mode, the warm-up counter prescaler divide ratio is 1/2
Wake up from STOP mode (OSCX or OSC)
In 200kHz RC oscillator mode, the warm-up counter prescaler divide ratio is 1/2
In 32.768kHz Crystal oscillator mode, the warm-up counter prescaler divide ratio is 1/2
14.2. If the “ Single Solar Supply Application selection” code option is equal to “ Disable ”, the warm-up timer interval is defined
as below.
Power-on Reset for OSCX or OSC
In 200kHz RC oscillator mode, the warm-up counter prescaler divide ratio is 1/2
In 32.768kHz Crystal oscillator mode, the warm-up counter prescaler divide ratio is 1/2
Pin Reset for OSCX or OSC
In 200kHz RC oscillator mode, the warm-up counter prescaler divide ratio is 1/2
In 32.768kHz Crystal oscillator mode, the warm-up counter prescaler divide ratio is 1/2
Wake up from STOP mode (OSCX or OSC)
In 200kHz RC oscillator mode, the warm-up counter prescaler divide ratio is 1/2
In 32.768kHz Crystal oscillator mode, the warm-up counter prescaler divide ratio is 1/2
Address
$15
$16
$17
$18
RDT.11
RDT.15
RDT.3
RDT.7
Bit 3
RDT.10
RDT.14
RDT.2
RDT.6
Bit 2
RDT.13
RDT.1
RDT.5
RDT.9
Bit 1
RDT.12
RDT.0
RDT.4
RDT.8
Bit 0
R/W
R/W ROM Data table address/data register
R/W ROM Data table address/data register
R/W ROM Data table address/data register
R/W ROM Data table address/data register
25
6
12
8
8
12
12
12
(64) (2.0ms).
(256) (1.3ms).
(256) (1.3ms).
(4096) (20.5ms).
(4096) (20.5ms).
(4096) (20.5ms).
(4096) (20.5ms).
14
10
10
14
14
14
14
(1024) (31.3ms).
(16384) (500ms).
(1024) (31.3ms).
(16384) (500ms).
(16384) (500ms).
(16384) (500ms).
(16384) (500ms).
Remarks
SH66L16A