74LVC86APW,118 NXP Semiconductors, 74LVC86APW,118 Datasheet - Page 2

• Manufacturer Part Number: 74LVC86APW,118
• Description: IC QUAD 2IN EXC-OR GATE 14TSSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVCr

Specifications of 74LVC86APW,118

• Number Of Circuits: 4
• Package / Case: 14-TSSOP
• Logic Type: XOR (Exclusive OR)
• Number Of Inputs: 2
• Current - Output High, Low: 24mA, 24mA
• Voltage - Supply: 2.7 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Product: OR
• Logic Family: LVC
• High Level Output Current: - 24 mA
• Low Level Output Current: 24 mA
• Propagation Delay Time: 3 ns
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 1.2 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Logical Function: XOR
• Number Of Elements: 4
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Temp Range: -40C to 125C
• Package Type: TSSOP
• Number Of Outputs: 1
• Technology: CMOS
• Mounting: Surface Mount
• Pin Count: 14
• Operating Temperature Classification: Automotive
• Quiescent Current: 40uA
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.2V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LVC86APW-T; 74LVC86APW-T; 935250110118

Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
FUNCTION TABLE
See note 1.
Note
1. H = HIGH voltage level;
2004 Mar 04
t
C
C
PHL
5 V tolerant inputs, for interfacing with 5 V logic
Supply voltage range from 1.2 to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltage up to 5.5 V
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from 40 to +85 C and 40 to +125 C.
I
PD
Quad 2-input EXCLUSIVE-OR gate
SYMBOL
P
f
f
C
V
N = total load switching outputs;
L = LOW voltage level.
i
o
/t
(C
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
2
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
V
CC
= 25 C; t
nA
f
H
H
o
L
L
2
) = sum of the outputs.
I
f
= GND to V
i
N + (C
r
= t
PARAMETER
f
2.5 ns.
L
CC
INPUT
.
V
CC
2
f
o
) where:
nB
H
H
L
L
2
C
V
DESCRIPTION
The 74LVC86A is a high-performance, low-power,
low-voltage, Si-gate CMOS device and superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 or 5 V devices. This
feature allows the use of these devices as translators in a
mixed 3.3 and 5 V environment.
The 74LVC86A provides the 2-input EXCLUSIVE-OR
function.
CC
L
D
= 50 pF; V
in W).
= 3.3 V; notes 1 and 2
CONDITIONS
CC
= 3.3 V
3.0
5.0
20
TYPICAL
OUTPUT
Product specification
nY
H
H
L
L
74LVC86A
ns
pF
pF
UNIT