dq8051xp Digital Core Design, dq8051xp Datasheet - Page 9

• Manufacturer Part Number: dq8051xp
• Manufacturer: Digital Core Design

are incremented every falling transition on their
corresponding input pins (T0, T1), if gates are
opened (GATE0, GATE1). T0, T1 input pins are
sampled every CLK period. It can be used as clock
source for UARTs.
Timer 2 – Second system timer module contains
one 16‐bit configurable timer: Timer 2 (TH2, TL2),
capture registers (RLDH, RLDL) and Timer 2 Mode
(T2MOD) register. It can work as a 16‐bit timer /
counter, 16‐bit auto‐reload timer / counter. It also
supports compare capture unit if it’s presented in
system. It can be used as clock source for UART0.
Compare Capture Unit – The compare / capture /
reload unit is one of the most powerful peripheral
units of the core. It can be used for all kinds of
digital signal generation and event capturing such
as pulse generation, pulse width modulation,
measurements etc.
Watchdog Timer – The watchdog timer is a 27‐bit
counter which is incremented every system clock
periods (CLK pin). It performs system protection
against software upsets.
UART0 – Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it can
transmit and receive concurrently. Includes Serial
Configuration register (SCON), serial receiver and
transmitter buffer (SBUF) registers. Its receiver is
double‐buffered, meaning it can commence recep‐
tion of a second byte before a previously received
byte has been read from the receive register. Writ‐
ing to SBUF0 loads the transmit register, and read‐
ing SBUF0 reads a physically separate receive reg‐
ister. It works in 3 asynchronous and 1 synchro‐
nous modes. UART0 can be synchronized by Timer
1 or Timer 2.
UART1 – Universal Asynchronous Receiver &
Transmitter module is full duplex, meaning it can
transmit and receive concurrently. Includes Serial
Configuration register (SCON1), serial receiver and
transmitter buffer (SBUF1) registers. Its receiver is
double‐buffered, meaning it can commence recep‐
tion of a second byte before a previously received
byte has been read from the receive register. Writ‐
ing to SBUF1 loads the transmit register, and read‐
ing SBUF1 reads a physically separate receive reg‐
ister. It works in 3 asynchronous and 1 synchro‐
nous modes. UART1 is synchronized by Timer 1.
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Master I2C Unit – I2C bus controller is a Master
module. The core incorporates all features re‐
quired by I2C specification. It supports both 7‐bit
and 10‐bit addressing modes on the I2C bus. It
works as a master transmitter and receiver. It can
be programmed to operate with arbitration and
clock synchronization to allow it operates in multi‐
master systems. Built‐in timer allows operation
from a wide range of the input frequencies. The
timer allows achieving any non‐standard clock
frequency. The I2C controller supports all trans‐
mission modes: Standard, Fast and High Speed up
to 3400 kbps.
Slave I2C Unit – I2C bus controller is a Slave mod‐
ule. The core incorporates all features required by
I2C specification. It works as a slave transmit‐
ter/receiver depending on working mode deter‐
mined by a master device. The I2C controller sup‐
ports all transmission modes: Standard, Fast and
High Speed up to 3400 kbs.
SPI Unit – it’s a fully configurable master/slave
Serial Peripheral Interface, which allows user to
configure polarity and phase of serial clock signal
SCK. It allows the microcontroller to communicate
with serial peripheral devices. It is also capable of
interprocessor communications in a multi‐master
system. A serial clock line (SCK) synchronizes shift‐
ing and sampling of the information on the two
independent serial data lines. SPI data are simulta‐
neously transmitted and received. SPI system is
flexible enough to interface directly with numer‐
ous standard product peripherals from several
manufacturers. Data rates as high as CLK/4. Clock
control logic allows a selection of clock polarity
and a choice of two fundamentally different clock‐
ing protocols to accommodate most available syn‐
chronous serial peripheral devices. When the SPI is
configured as a master, software selects one of
four different bit rates for the serial clock. SPI
automatically drives slave select outputs SSO[7:0],
and address SPI slave device to exchange serially
shifted data. Error‐detection logic is included to
support interprocessor communications. A write‐
collision detector indicates when an attempt is
made to write data to the serial shift register while
a transfer is in progress. A multiple‐master mode‐
fault detector automatically disables SPI output