dq8051xp Digital Core Design, dq8051xp Datasheet - Page 3

• Manufacturer Part Number: dq8051xp
• Manufacturer: Digital Core Design

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rate between HAD and Silicon
Code execution breakpoints
Hardware execution watch‐points at
Hardware watch‐points activated at a certain
Automatic adjustment of debug data transfer speed
JTAG Communication interface
Power Management Unit
Power management mode
Switchback feature
Stop mode
Extended Interrupt Controller
2 priority levels
Up to 7 external interrupt sources
Up to 8 interrupt sources from peripherals
Four 8‐bit I/O Ports
Bit addressable data direction for each line
Read/write of single line and 8‐bit group
Three 16‐bit timer/counters
Timers clocked by internal source
Auto reload 8/16‐bit timers
Externally gated event counters
Two full‐duplex serial ports
Synchronous mode, fixed baud rate
8‐bit asynchronous mode, fixed baud rate
9‐bit asynchronous mode, fixed baud rate
9‐bit asynchronous mode, variable baud rate
I2C bus controller ‐ Master
7‐bit and 10‐bit addressing modes
NORMAL, FAST, HIGH speeds
Multi‐master systems supported
Clock arbitration and synchronization
User defined timings on I2C lines
Wide range of system clock frequencies
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Program Memory
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
two real‐time PC breakpoint
unlimited number of real‐time OPCODE breakpoints
Internal (direct) Data Memory
Special Function Registers (SFRs)
External Data Memory
address by any write into memory
address by any read from memory
address by write into memory a required data
address by read from memory a required data
All trademarks mentioned in this document are trademarks of their respective owners.
Copyright© 1999‐2011 DCD – Digital Core Design. All Rights Reserved
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face
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standard single precision
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standard single precision real, word and short in‐
tegers
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frequencies (build‐in 5‐bit timer)
Interrupt generation
I2C bus controller ‐ Slave
NORMAL speed 100 kbs
FAST speed 400 kbs
HIGH speed 3400 kbs
Wide range of system clock frequencies
User defined data setup time on I2C lines
Interrupt generation
SPI – Master and Slave Serial Peripheral Inter‐
Supports speeds up ¼ of system clock
Four transfer formats supported
System errors detection
Allows operation from a wide range of system clock
Interrupt generation
Programmable Watchdog Timer
16‐bit Compare/Capture Unit
Events capturing
Pulses generation
Digital signals generation
Gated timers
Sophisticated comparator
Pulse width modulation
Pulse width measuring
Fixed‐Point arithmetic coprocessor
Multiplication ‐ 16bit
Multiplication ‐ 32bit
Division ‐ 32bit / 32bit
Division ‐ 16bit / 16bit
Floating‐Point arithmetic coprocessor IEEE‐754
FADD, FSUB ‐ addition, subtraction
FMUL, FDIV‐ multiplication, division
FSQRT‐ square root
FUCOM ‐ compare
FCHS ‐ change sign
FABS ‐ absolute value
Floating‐Point math coprocessor ‐ IEEE‐754
FADD, FSUB‐ addition, subtraction
FMUL, FDIV‐ multiplication, division
FSQRT‐ square root
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Mode fault error
Write collision error
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16bit
32bit