HEF4011BT,653 NXP Semiconductors, HEF4011BT,653 Datasheet - Page 5

• Manufacturer Part Number: HEF4011BT,653
• Description: IC GATE NAND QUAD 2INPUT SO14
• Manufacturer: NXP Semiconductors
• Series: 4000Br

Specifications of HEF4011BT,653

• Number Of Circuits: 4
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Logic Type: NAND Gate
• Number Of Inputs: 2
• Current - Output High, Low: 2.4mA, 2.4mA
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Product: NAND
• Logic Family: HEF4000
• High Level Output Current: - 3.6 mA
• Low Level Output Current: 3.6 mA
• Propagation Delay Time: 20 ns
• Supply Voltage (max): 15.5 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Logical Function: NAND
• Number Of Elements: 4
• Operating Supply Voltage (typ): 3.3/5/9/12V
• Operating Temp Range: -40C to 125C
• Package Type: SO
• Number Of Outputs: 1
• Technology: CMOS
• Mounting: Surface Mount
• Pin Count: 14
• Operating Temperature Classification: Automotive
• Quiescent Current: 1uA
• Operating Supply Voltage (max): 15V
• Operating Supply Voltage (min): 3V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 933372640653; HEF4011BTD-T; HEF4011BTD-T

NXP Semiconductors
11. Dynamic characteristics
Table 7.
T
[1]
[2]
Table 8.
V
HEF4011B
Product data sheet
Symbol Parameter
t
t
t
Symbol Parameter
P
pd
THL
TLH
amb
SS
D
= 0 V; t
The typical value of the propagation delay and output transition time can be calculated with the extrapolation formula (C
t
pd
= 25
is the same as t

propagation delay
HIGH to LOW output transition time 10 + 1.00  C
LOW to HIGH output transition time 10 + 1.00  C
dynamic power dissipation
C; for waveforms see
r
Dynamic characteristics
Dynamic power dissipation
= t
f

20 ns; T
PLH
and t
amb
PHL
= 25
.
Figure

C.
V
10 V P
15 V P
4; for test circuit see
5 V P
DD
All information provided in this document is subject to legal disclaimers.
Typical formula
28 + 0.55  C
D
D
D
Extrapolation formula
14 + 0.23  C
12 + 0.16  C
9 + 0.42  C
6 + 0.28  C
9 + 0.42  C
6 + 0.28  C
= 20100  f
= 1300  f
= 6000  f
Rev. 4 — 30 March 2011
i
i
Figure
+ (f
+ (f
i
L
L
L
L
L
L
L
L
L
+ (f
o
o
o
 C
 C
5; unless otherwise specified.
 C
L
L
[1]
)  V
)  V
L
)  V
DD
DD
V
10 V
15 V
10 V
15 V
10 V
15 V
DD
5 V
5 V
5 V
DD
2
2
2
(W) f
(W)
(W)
[2]
Where
f
C
(f
V
i
o
DD
L
= input frequency in MHz;
Min
-
-
-
-
-
-
-
-
-
= output frequency in MHz;
o
= output load capacitance in pF;
 C
= supply voltage in V.
Quad 2-input NAND gate
L
) = sum of the outputs;
Typ
55
25
20
60
30
20
60
30
20
HEF4011B
© NXP B.V. 2011. All rights reserved.
Max
110
120
120
45
35
60
40
60
40
L
in pF).
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
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