74LVC02APW,118 NXP Semiconductors, 74LVC02APW,118 Datasheet - Page 2
![IC QUAD 2-IN NOR GATE 14-TSSOP](/photos/6/58/65814/568-14-tssop_sot402-1_sml.jpg)
74LVC02APW,118
Manufacturer Part Number
74LVC02APW,118
Description
IC QUAD 2-IN NOR GATE 14-TSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet
1.74LVC02AD118.pdf
(15 pages)
Specifications of 74LVC02APW,118
Number Of Circuits
4
Package / Case
14-TSSOP
Logic Type
NOR Gate
Number Of Inputs
2
Current - Output High, Low
24mA, 24mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Product
NOR
Logic Family
74LVC
High Level Output Current
- 24 mA
Low Level Output Current
24 mA
Propagation Delay Time
14 ns
Supply Voltage (max)
3.6 V
Supply Voltage (min)
1.2 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Logical Function
NOR
Number Of Elements
4
Operating Supply Voltage (typ)
1.8/2.5/3.3V
Operating Temp Range
-40C to 125C
Package Type
TSSOP
Number Of Outputs
1
Technology
CMOS
Mounting
Surface Mount
Pin Count
14
Operating Temperature Classification
Automotive
Quiescent Current
40uA
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.2V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
568-2271-2
74LVC02APW-T
935250010118
74LVC02APW-T
935250010118
Philips Semiconductors
FEATURES
QUICK REFERENCE DATA
GND = 0 V; T
Notes
1. C
2. The condition is V
ORDERING INFORMATION
2004 Mar 12
t
C
C
74LVC02AD
74LVC02ADB
74LVC02APW
74LVC02ABQ
PHL
5 V tolerant inputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
Inputs accept voltages up to 5.5 V
Complies with JEDEC standard no. 8-1A
ESD protection:
HBM EIA/JESD22-A114-A exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V.
Specified from
I
PD
Quad 2-input NOR gate
40 C to +85 C and 40 C to +125 C.
SYMBOL
P
f
f
C
V
N = total load switching outputs;
i
o
/t
(C
D
CC
PD
= input frequency in MHz;
L
PLH
= output frequency in MHz;
= output load capacitance in pF;
= C
TYPE NUMBER
L
is used to determine the dynamic power dissipation (P
= supply voltage in Volts;
PD
V
CC
amb
2
V
CC
= 25 C; t
propagation delay nA, nB to nY
input capacitance
power dissipation capacitance per gate
f
o
2
) = sum of the outputs.
I
f
= GND to V
i
N + (C
r
= t
f
PARAMETER
2.5 ns.
TEMPERATURE RANGE
L
CC
.
V
40 C to +125 C
40 C to +125 C
40 C to +125 C
40 C to +125 C
CC
2
f
o
) where:
2
DESCRIPTION
The 74LVC02A is a high-performance, low-power,
low-voltage, Si-gate CMOS device, superior to most
advanced CMOS compatible TTL families.
Inputs can be driven from either 3.3 V or 5 V devices. This
feature allows the use of these devices as translators in
a mixed 3.3 V and 5 V environment.
The 74LVC02A provides the 2-input NOR function.
D
C
V
notes 1 and 2
CC
L
in W).
= 50 pF; V
PINS
= 3.3 V;
14
14
14
14
CONDITIONS
PACKAGE
CC
DHVQFN14
PACKAGE
TSSOP14
SSOP14
= 3.3 V
SO14
2.3
4.0
10
MATERIAL
TYPICAL
plastic
plastic
plastic
plastic
Product specification
74LVC02A
ns
pF
pF
SOT108-1
SOT337-1
SOT402-1
SOT762-1
CODE
UNIT