saa8115hl NXP Semiconductors, saa8115hl Datasheet - Page 12
saa8115hl
Manufacturer Part Number
saa8115hl
Description
Saa8115hl-04 Digital Camera Usb Interface
Manufacturer
NXP Semiconductors
Datasheet
1.SAA8115HL.pdf
(51 pages)
- Current page: 12 of 51
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Philips Semiconductors
9397 750 07395
Product specification
Fig 4. USB video FIFO.
8.7 PSIE-MMU, I
8.8 ATX interface
READ_SPACING determines the read rate. Its value can easily be determined with
the formula:
The Programmable Serial Interface Engine (PSIE) and Memory Management
Unit (MMU) is the heart of the USB protocol hardware (see
actual packets that are transferred to the USB and passes the incoming packets to
the right end-point buffers. These buffers are allocated as part of the USB RAM
space.
The microcontroller communicates via the I
protocol distinguishes three register spaces. These spaces are addressed via
different commands. The command is sent to the command address.
Depending on the command it is sent to the PSIE-MMU and/or to the command
interpreter which configures the (de-)mux to open the path to the right register space.
Subsequent write/reads to/from the data address store or retrieve data from the
register space selected by the command.
The SAA8115HL contains an analog bus driver, called the ATX. It incorporates a
differential and two single-ended receivers and a differential transmitter.
The interface to the bus consists of a differential data pair (ATXDM and ATXDP).
READ_SPACING
data from transfer buffer
write
WRITE
SYNC
2
Ptr_to_start_Vframe
C-bus interface and USB RAM space
Rev. 04 — 10 August 2000
<
--------------------------------------- -
PACKET_SIZE
FIFO
12000
data to PSIE-MMU
read
enable
read
READ_SPACING
FIFO_OFFSET
PACKET_SIZE
FIFO_ACTIVE
2
C-bus with the PSIE-MMU. The I
FCE431
Digital camera USB interface
SAA8115HL
Figure
© Philips Electronics N.V. 2000. All rights reserved.
5). It formats the
2
C-bus
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