k9k1208u0a Samsung Semiconductor, Inc., k9k1208u0a Datasheet - Page 23

• Manufacturer Part Number: k9k1208u0a
• Description: 64m X 8 Bit Nand Flash Memory
• Manufacturer: Samsung Semiconductor, Inc.

K9K1208U0A-YCB0, K9K1208U0A-YIB0
COPY-BACK PROGRAM
The copy-back program is configured to quickly and efficiently rewrite data stored in one page within the array to another page within
the same array without utilizing an external memory. Since the time-consuming sequently-reading and its re-loading cycles are
removed, the system performance is improved. The benefit is especially obvious when a portion of a block is updated and the rest of
the block also need to be copied to the newly assigned free block. The operation for performing a copy-back is a sequential execu-
tion of page-read without burst-reading cycle and copying-program with the address of destination page. A normal read operation
with "00h" command with the address of the source page moves the whole 528byte data into the internal buffer. As soon as the Flash
returns to Ready state, copy-back programming command "8Ah" may be given with three address cycles of target page followed.
The data stored in the internal buffer is then programmed directly into the memory cells of the destination page. Once the Copy-Back
Program is finished, any additional partial page programming into the copied pages is prohibited before erase. Since the memory
array is internally partitioned into four different planes, copy-back program is allowed only within the same memory plane. Thus, A14
and A25, the plane address, of source and destination page address must be the same.
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in two cycles initiated by an Erase
Setup command(60h). Only address A
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 8 details the sequence.
Figure 9. Block Erase Operation
R/B
I/O
Figure 8. Copy-Back Program Operation
R/B
I/O
0
0
~
~
7
7
00h
60h
A
Source Address
0
Add.(4Cycles)
~ A
7
& A
Block Add. : A
Address Input(3Cycle)
9
~ A
25
14
to A
9
t
R
~ A
25
25
is valid while A
8Ah
D0h
Destination Address
A
0
9
Add.(4Cycles)
23
~ A
to A
7
& A
13
t
BERS
is ignored. The Erase Confirm command(D0h) following the
9
~ A
25
t
PROG
70h
FLASH MEMORY
70h
I/O
Fail
Fail
I/O
0
0
Pass
Pass