cl-ps6700 Cirrus Logic, Inc., cl-ps6700 Datasheet - Page 12

• Manufacturer Part Number: cl-ps6700
• Description: Low-power Pc Card Controller For The Cl-ps7111
• Manufacturer: Cirrus Logic, Inc.

2.1.2 Access Control Signals
Signal
PCE_L
PTYPE
PRDY
12
PIN DESCRIPTIONS
Type
I/O
I
I
Source
Power
sys
sys
sys
Description
PC Card Chip Enable: This signal, if asserted, enables the strobing of address and data informa-
tion between the CL-PS7111 and the CL-PS6700 through the MD bus. For a read from PC Card
memory or I/O space, the CL-PS7111 asserts PCE_L during the address phase and (possibly
much later) during the data phase of a read transaction. Depending on the transaction, PCE_L is
low for between two and five PCLK periods. When a read is pending, the CL-PS7111 waits for
PRDY from the CL-PS6700 to complete the data phase. If the CL-PS6700 does not respond within
a given time period, the CL-PS7111 times out and performs a dummy data phase by asserting
PCE_L without receiving PRDY, causing the CL-PS6700 to abort the card read. If the CL-PS6700
times out card writes, it issues a WR_FAIL interrupt.
PC Card Transaction Type: During the first clock of PCE_L, this signal indicates whether the oper-
ation is a write or a read. A low level indicates a write and a high level indicates a read. During the
second clock of the address phase, this signal indicates if the transaction was initiated by the CPU
or an optional DMA controller. A low level indicates the DMA controller, and a high level indicates
the CPU. If initiated by the DMA controller and the address targets the card’s I/O space, a properly
configured CL-PS6700 performs a DMA transfer at the card. This feature is not supported by the
CL-PS7111 and is for future use only.
NOTE: PRDY should be pulled up with a 100-k resistor.
PC Card ready: This signal goes to the CL-PS7111 and serves as both an address ready and data
ready signal. It can also indicate a busy (card RDY/BUSY pin) status of the corresponding PC Card
socket (see configuration bit “Include Card Ready in PRDY”). Normally, the CL-PS6700 leaves this
signal asserted (high). When the CL-PS7111 targets a read or write transaction to the CL-PS6700,
the CL-PS6700 deasserts PRDY in the second clock of the address phase until it has processed
the transaction.
For a card write, PRDY remains deasserted only if the write queue becomes full due to the current
transaction. Otherwise, PRDY is reasserted during the next clock. When the CL-PS6700 write
queue is full, PRDY is reasserted only after a queued write is disassembled (if necessary) and
propagated to the PC Card socket, freeing an entry in the write queue. Therefore, the CL-PS7111
is assured that it does not get data wait states for card write operations.
For a card read, the CL-PS6700 asserts PRDY when it has collected the required bytes from the
PC Card. The CL-PS7111 then initiates the data phase by issuing a second PCE_L without driving
the MD bus to the CL-PS6700(s). Then, the CL-PS6700 with a posted read responds with the read
data.
The CL-PS6700 registers can be read regardless of the state of PRDY. Therefore, PRDY cannot
toggle during the address phase of register access if it is already deasserted. PRDY is a don’t care
input to the CL-PS7111 during the four (for write) or five (for read) clocks of register accesses.
C
Table 2-4.
Cycle 1 (RD/WR) Cycle 2 (CPU/DMA)
I R R U S
PTYPE during Address Phase
0
0
1
1
L
O G I C
PTYPE Signal Encoding During PCE_L
C
O N F I D E N T I A L
0
1
0
1
, N D A R
PRELIMINARY DATA BOOK v1.0
Write operation initiated by DMA controller.
Write operation initiated by CPU.
Read operation initiated by DMA controller.
Read operation initiated by CPU.
E Q U I R E D
MD Bus Transfer Type
Low-Power PC Card Controller
November 1997
CL-PS6700