CL-PD6720 Cirrus Logic, Inc., CL-PD6720 Datasheet
CL-PD6720
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CL-PD6720 Summary of contents
Page 1
... With the CL-PD6712, a complete PC Card solution with power-control logic can occupy less than 1.5 square inches (excluding the socket connector). With the CL-PD6720 or CL-PD6722, a complete dual- socket PC Card solution with power-control logic can occupy less than 2 square inches (excluding socket connectors). ...
Page 2
... Host Adapter Form Factor 1 3/8" CL-PD6712 144-Pin VQFP 2 CL-PD6712 and CL-PD672X is a superset of the Intel 82365SL register set. The chips provide fully buffered PC Card interfaces, meaning that no external logic is required for buffer- ing signals to/from the interface, and power con- sumption can be controlled by limiting signal transitions on the PC Card bus ...
Page 3
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters For the CL-PD6720, this data sheet applies to Revision D and above. For data on an earlier revision of the CL-PD6720, please use Version 2.5 of the CL-PD6710/PD672X Data Sheet. 1. GENERAL CONVENTIONS.................. 7 2. PIN INFORMATION ............................... 8 2.1 Pin Diagrams ..................................................... 9 2.2 Pin Description Conventions............................ 11 2 ...
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... Programming the DMA Request Pin from the Card........................................................ 85 14.4.2 Configuring the Socket Interface for I/O ....... 86 14.4.3 Preventing Dual Interpretation of DMA Handshake Signals....................................... 86 14.4.4 Turning On DMA System .............................. 86 14.5 The DMA Transfer Process .............................. 86 14.6 Terminal Count to Card at Conclusion of Transfer ....................................................... 86 4 TABLE OF CONTENTS CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters 15. ELECTRICAL SPECIFICATIONS ....... 87 15.1 Absolute Maximum Ratings ............................. 87 15.2 DC Specifi ...
Page 5
... A new chip was added: the CL-PD6712, which replaces the CL-PD6710. Extended register set was expanded. 208-pin VQFP package option was added for the CL-PD6720 and CL-PD6722. Some windowing register names were changed to specify either card or system. References to PCMCIA card were changed to PC Card ...
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... CL-PD6722 register set. Section 1.2 Description for bits labeled Reserved, Compatibil- ity and Scratchpad have been clarified. 5.2 In the table for “Bits 1-0: Battery Voltage Detect”, the column headings for bit 1 and bit 0 were reversed, and have been corrected. ...
Page 7
... The following general conventions apply to this doc- ument. Throughout this document, CL-PD67XX means CL-PD6712, CL-PD6720, and CL-PD6722. Like- wise, CL-PD672X means CL-PD6720 and CL-PD6722. Bits within words and words within various memory spaces are generally numbered with a 0 (zero) as the least-significant bit or word. For example, the least-signifi ...
Page 8
... General-purpose strobe / voltage sense pins Power control pins Power and ground pins Refer to Figure 2-1 for the CL-PD6712 and Figure 2-2 for the CL-PD6720 and CL-PD6722 pin diagrams. The pin assignments for the groups of interface pins are shown in Table 2-1 through Table 2-5. 8 PIN INFORMATION CL-PD6712/’ ...
Page 9
... IRQ9 138 SD6 139 SD7 140 PWRGOOD 141 SPKR_OUT*/C_SEL 142 -INTR 143 VS2#/B_GPSTB +5V 144 September 1995 PRELIMINARY DATA SHEET v3.0 ISA_VCC CL-PD6712 144-Pin VQFP Figure 2-1. CL-PD6712 Pin Diagram 72 GND 71 SD15 70 -CD2 69 WP/-IOIS16 D10 ...
Page 10
... B_VPP_PGM 204 B_VPP_VCC 205 B_-VCC_3 206 207 B_-VCC_5 208 +5V +5V Figure 2-2. CL-PD6720 and CL-PD6722 Pin Diagram 10 PIN INFORMATION B_SOCKET_VCC CL-PD6720 and CL-PD6722 208-Pin PQFP or VQFP A_SOCKET_VCC PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters B_A22 ...
Page 11
... The I/O-type code (I/O) column indicates the input and output configurations of the pins on the CL-PD67XX.The possible types are defined below. The power-type code (Pwr.) column indicates the output drive power source for an output pin or the pull-up power source for an input pin on the CL-PD67XX. The possible types are defined below. I/O Type Description ...
Page 12
... Address Latch Enable: A high on this input indicates a valid memory address on the LA[23:17] bus lines. Connect to ISA signal BALE. 12 PIN INFORMATION CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Pin Number Qty. CL-PD6720/ CL-PD6712 CL-PD6722 96, 94, 92, 89, 157, 155, 153, 87, 85, 84 151, 149, 147, 146 7 123:120, 118, ...
Page 13
... ISA bus DACK* line corresponding to the ISA bus DREQ line that the IRQ10 pin is connected to. In DMA mode this signal is active-low. September 1995 PRELIMINARY DATA SHEET v3.0 (cont.) Pin Number CL-PD6720/ CL-PD6712 CL-PD6722 141 201 126 187 99 ...
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... ZWS* Zero Wait State: This output is connected to the ISA ZWS (0WS) signal driven low by the CL-PD67XX when it is able to complete the current memory access cycle in zero wait states. 14 PIN INFORMATION (cont.) Pin Number CL-PD6720/ CL-PD6712 CL-PD6722 95 156 90 152 88 150 143 ...
Page 15
... This supply pin can be set CC to 3.3 or 5.0 V. The ISA Bus Interface pin group (this table) operates at the voltage applied to this pin independent of the voltage applied to other pin groups. September 1995 PRELIMINARY DATA SHEET v3.0 (cont.) Pin Number CL-PD6720/ CL-PD6712 CL-PD6722 142 202 102 163 4 3 76, 135 138, 195 Qty ...
Page 16
... To differentiate the sockets, all CL-PD6720 and CL-PD6722 pin names have either prepended to the pin names indicated. For example, A_A[25:0] and B_A[25:0] are the independent address buses to the sockets. 2 When a socket is configured as an ATA drive interface, socket interface pin functions change. See Table 11-1 on page 75. ...
Page 17
... To differentiate the sockets, all CL-PD6720 and CL-PD6722 pin names have either prepended to the pin names indicated. For example, A_A[25:0] and B_A[25:0] are the independent address buses to the sockets. 2 When a socket is configured as an ATA drive interface, socket interface pin functions change ...
Page 18
... IRQ15/RI_OUT* is configured for RI Out (see page 62 differentiate the sockets, all CL-PD6720 and CL-PD6722 pin names have either prepended to the pin names indicated. For example, A_A[25:0] and B_A[25:0] are the independent address buses to the sockets. 2 When a socket is configured as an ATA drive interface, socket interface pin functions change. See Table 11-1 on page 75. ...
Page 19
... CL-PD67XX pin groups differentiate the sockets, all CL-PD6720 and CL-PD6722 pin names have either prepended to the pin names indicated. For example, A_A[25:0] and B_A[25:0] are the independent address buses to the sockets. 2 When a socket is configured as an ATA drive interface, socket interface pin functions change ...
Page 20
... Pin Number CL-PD6720/CL-PD6722 CL-PD6712 Socket pin Pin Number CL-PD6720/ CL-PD6712 CL-PD6722 1 208 16, 91 27, 133 20, 54, 72, 78, 31, 70, 79, 128, 133 111, 140, 192 PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Qty. I/O Pwr ...
Page 21
... A ‘1’ on the SPKR_OUT*/C_SEL pin will cause the device to address Socket 0 (and Socket 1 for the CL-PD6720 and CL-PD6722). A ‘0’ on this pin will cause the device to address Socket 2 (and Socket 3 for the CL-PD6720 and CL-PD6722). ...
Page 22
... Common memory can be used by host software for any purpose (such as flash file system, system memory, and floppy emulation). 1 The CL-PD67XX is backward-compatible with PCMCIA standards 1.0, 2.0, 2.01, and 2.1. The CL-PD67XX is also compatible with JEIDA 4.1 and its earlier standards corresponding with the PCMCIA standards above. 22 INTRODUCTION CL-PD6712/’ ...
Page 23
... The timing of accesses (Setup/Command/Recovery) can be set by either of two timing register sets: Timing Timer Set 0 or Timer Set 1. CAUTION: The windows of the CL-PD67XX should never be allowed to overlap with each other or the other devices in the system. This would cause collisions in the IOCS16*, MEMCS16*, IOCHRDY, and SD[15:0] sig- nals, resulting in erratic behavior. ...
Page 24
... Card Memory Map Offset Address Registers 64 Kbytes Card I/O Map I/O Window Offset Address Registers Figure 3-2. I/O Window Organization PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters PC Card Memory Address Space 64 Mbytes Common Memory Attribute Memory Card Memory Window NOTE: ISA memory window can map to either common or attribute PC Card memory ...
Page 25
... Registers Offset Write FIFO Figure 3-3. Functional Block Diagram Either class of interrupts can be routed to any of the ten interrupt pins on the CL-PD67XX. Connection of Interrupt Pins IRQ interrupts in PC-compatible systems are not generally shared by hardware. Therefore, each device in the system using IRQ interrupts must have a unique interrupt line ...
Page 26
... Alternate Functions of Interrupt Pins The CL-PD6720 has two interrupt pins that can IRQ12/LED_OUT* and IRQ15/RI_OUT*. In addi- tion, the CL-PD6712 and CL-PD6722 allow IRQ9 and IRQ10 to be programmed for system DMA transfer handshake functions. ...
Page 27
... VS2 pins Card socket to allow card services and socket services software to sense card operating voltage ranges. The CL-PD6720 and CL-PD6722 can also be sim- ply configured for dual-socket VS1 and VS2 detec- tion with an external read port consisting of half of a ’ ...
Page 28
... Static 1 – High – – – If the CL-PD67XX has been set for automatic power- on (Power Control register bits 4 and 5 are both ‘1’s), the CL-PD67XX automatically enables the socket V ply). If the CL-PD67XX has been programmed to cause management interrupts for card-detection events, ...
Page 29
... Data bus (D[7:0]). 3.1.12 Programmable PC Card Timing The Setup, Command, and Recovery time for the PC Card bus is programmable (see Chapter 10). The CL-PD67XX can be programmed to match the tim- ing requirements of any PC Card. There are two sets of timing registers, Timer Set 0 and Timer Set 1, that SBHE* ...
Page 30
... The floppy disk drives ISA-data-bus bit read from 3F7h, and the hard disk drives bits 6:0. To allow both floppy disk control- lers on the motherboard and hard disks on the PC Card bus (or vice versa) to coexist, the CL-PD67XX Figure 3-4. Indexed 8-Bit Register Structure 30 INTRODUCTION ...
Page 31
... The application of the RESET signal (see page 18) on power-up causes initialization of all the CL-PD67XX register bits and fields to their reset val- ues. Not all registers have reset values; only regis- ters with bits and fields specified to have reset values are initialized ...
Page 32
... When the register is socket-specific, the Index value given in the register heading is for Socket A only. For the Socket B register on the CL-PD6720 and CL-PD6722, add 40h to the Index value of the Socket A register. Special Function Bits Following is a description of bits with special func- ...
Page 33
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters 5. OPERATION REGISTERS The CL-PD67XX’s internal registers are accessed through a pair of Operation registers — an Index reg- ister and a Data register. The Index register is accessed at address 03E0h, and the Data register is accessed at 03E1h. ...
Page 34
... Chapter 9: b Extension 1Fh 20h 60h 21h 61h Chapter 8: 22h 62h Memory Window 23h 63h Mapping 24h 64h 25h 65h PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 Page Number ...
Page 35
... Card I/O Map 1 Offset Address High Setup Timing 0 Command Timing 0 Recovery Timing 0 Setup Timing 1 Command Timing 1 Recovery Timing 1 a Socket B is available on the dual-socket CL-PD6720 and CL-PD6722. b This register affects both sockets (it is not specific to either socket). September 1995 PRELIMINARY DATA SHEET v3.0 Index Value Chapter a ...
Page 36
... The Data register is accessed at at 03E1h. This register indicates the contents of the register at the Device/Socket/Register Index selected by the Index register. 36 OPERATION REGISTERS Bit Bit Bit Data PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Register Per: chip Register Compatibility Type: 365 Bit Bit Bit September 1995 ...
Page 37
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters 6. CHIP CONTROL REGISTERS 6.1 Chip Revision Register Name: Chip Revision Index: 00h Bit Bit 7 6 Interface ID R:10 a Value for the current stepping only. Bits 3:0 — Revision This field indicates compatibility with the 82365SL A-step. ...
Page 38
... Bit 3 Bit 2 High 0 0 Low 0 1 High 1 0 Low 1 1 PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Register Per: socket Register Compatibility Type: 365 Bit Bit 2 1 -CD1 BVD2 Battery Voltage Detect Card Interpretation ...
Page 39
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Bit 5 — Ready/Busy* 0 Card is not ready. 1 Card is ready. This bit indicates the state of the RDY/-IREQ pin (see page 17) on the card. If the card has been configured for I/O, then this bit will not be valid. ...
Page 40
... Inactive high Inactive low Activated per Activated per Power Control Misc Control 1 register, register, bit 1 bits 1 and 0 Inactive high Inactive low Activated per Activated per Power Control Misc Control 1 register, register, bit 1 bits 1 and 0 CL-PD67XX Signal Outputs to Socket September 1995 Bit 0 and ...
Page 41
... V and V CC active low. When this bit is set to ‘1’, the CL-PD67XX causes power to the card to be turned on and off automatically with the insertion and removal card from the socket. Bit 7 — Card Enable 0 Outputs to card socket are not enabled and are floating. ...
Page 42
... Reserved 0111 IRQ 7 1000 Reserved 1001 IRQ 9 (On the CL-PD67X2, this output may alternately be used as an ISA bus DACK* signal) 1010 IRQ 10 (On the CL-PD67X2, this output may alternately be used as an ISA bus DRQ signal) 1011 IRQ 11 1100 IRQ 12 (This output may alternately be used for LED) ...
Page 43
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Bit 6 — Card Reset* 0 The RESET signal to the card socket is set active (high for normal, low for ATA mode). 1 The RESET signal to the card socket is set inactive (low for normal, high for ATA mode). ...
Page 44
... R:0 R:0 This register indicates the source of a management interrupt generated by the CL-PD67XX. NOTE: The corresponding bit in the Management Interrupt Configuration register must be set to ‘1’ to enable each specific status change detection. Bit 0 — Battery Dead Or Status Change 0 A transition (from high to low for memory card support or either high to low or low to high for I/O card support) on the BVD1/-STSCHG pin has not occurred since this register was last read ...
Page 45
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters 6.6 Management Interrupt Configuration Register Name: Management Interrupt Configuration Index: 05h Bit Bit 7 6 Management IRQ Select RW:0000 This register controls which status changes may cause management interrupts and at which pin the man- agement interrupts will appear. Bit 0 — ...
Page 46
... Reserved 0111 IRQ 7 1000 Reserved 1001 IRQ 9 (On the CL-PD67X2, this output may alternately be used as an ISA bus DACK* signal) 1010 IRQ 10 (On the CL-PD67X2, this output may alternately be used as an ISA bus DRQ signal) 1011 IRQ 11 1100 IRQ 12 (This output may alternately be used for LED) ...
Page 47
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters 6.7 Mapping Enable Register Name: Mapping Enable Index: 06h Bit Bit 7 6 I/O Map 1 I/O Map 0 MEMCS16 Full Enable Enable Decode RW:0 RW:0 RW:0 Bit 0 — Memory Map 0 Enable 0 Memory Mapping registers for Memory Space 0 disabled. 1 Memory Mapping registers for Memory Space 0 enabled. ...
Page 48
... I/O Mapping registers for I/O Space 1 enabled. When this bit is ‘1’, the I/O Mapping registers for I/O Space 1 will be enabled and the controller will respond to I/O accesses in the I/O space defined by those registers. 48 CHIP CONTROL REGISTERS CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters September 1995 PRELIMINARY DATA SHEET v3.0 ...
Page 49
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters 7. I/O WINDOW MAPPING REGISTERS The I/O windows must never include 3E0h and 3E1h. 7.1 I/O Window Control Register Name: I/O Window Control Index: 07h Bit Bit 7 6 Timing Compatibility Auto-Size I/O Register Bit Window 1 Select 1 RW:0 RW:0 RW:0 Bit 0 — I/O Window 0 Size 0 8-bit data path to I/O Window 0 ...
Page 50
... Start Address 7:0 RW:00000000 Bit Bit Bit Start Address 15:8 RW:00000000 PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Register Per: socket Register Compatibility Type: 365 Bit Bit Bit Register Per: socket Register Compatibility Type: 365 Bit ...
Page 51
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters 7.4 System I/O Map 0–1 End Address Low Register Name: System I/O Map 0–1 End Address Low Index: 0Ah, 0Eh Bit Bit 7 6 There are two separate System I/O Map End Address Low registers, each with identical fields. These reg- ...
Page 52
... Offset Address 7:1 RW:0000000 Bit Bit Bit Offset Address 15:8 RW:00000000 PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Register Per: socket Register Compatibility Type: ext. Bit Bit Bit RW:0 Register Per: socket Register Compatibility Type: ext. ...
Page 53
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters 8. MEMORY WINDOW MAPPING REGISTERS The following information about the memory map windows is important: The memory window mapping registers determine where in the ISA memory space and PC Card memory space accesses will occur. There are five memory windows that can be used independently. ...
Page 54
... Scratchpad Bits RW:00 Bit Bit Bit End Address 19:12 RW:00000000 PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Register Per: socket Register Compatibility Type: 365 Bit Bit Bit Start Address 23:20 RW:0000 Register Per: socket Register Compatibility Type: 365 ...
Page 55
... Selects Timer Set 0. 01 Selects Timer Set 1. 10 Selects Timer Set 1. 11 Selects Timer Set 1. This field selects the timer set. Timer Set 0 and 1 reset to values compatible with standard ISA and three-wait-state cycles (see page 72). September 1995 PRELIMINARY DATA SHEET v3.0 Bit Bit Bit 5 4 ...
Page 56
... Offset Address 19:12 RW:00000000 Bit Bit Bit Offset Address 25:20 RW:000000 PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Register Per: socket Register Compatibility Type: 365 Bit Bit Bit Register Per: socket Register Compatibility Type: 365 Bit ...
Page 57
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Bits 5:0 — Offset Address 25:20 This field contains the most-significant six bits of the Offset Address. See the description of the Offset Address field associated with bits 7:0 of the Card Memory Map 0–4 Offset Address Low register (see page 56). Bit 6 — ...
Page 58
... Bit 7 6 Inpack Enable Scratchpad Bits RW:0 RW:00 a May be used on some versions of the CL-PD672X to read levels of the A_GPSTB and B_GPSTB pins. Contact Cirrus Logic for more information. Bit 1 — -VCC_5 activated when card power applied. 1 -VCC_3 activated when card power applied. ...
Page 59
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Bit 3 — Pulse System IRQ 0 RDY/-IREQ generated interrupts are passed to the IRQ[XX] pin as level-sensitive. 1 When a RDY/-IREQ interrupt occurs, the IRQ[XX] pin is driven with the pulse train shown in Figure 9-1 and allows for interrupt sharing. ...
Page 60
... CC 60 EXTENSION REGISTERS Bit Bit Bit Scratchpad Bits RW:0000000 PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Register Per: socket Register Compatibility Type: ext. Bit Bit I/O Write No operation occurs; default on reset Flush the FIFO September 1995 ...
Page 61
... Selects input thresholds for use when 5.0 volts is connected to the CL-PD67XX CORE_VDD pins. This bit selects input threshold circuits for use when 3.3 or 5.0 volts is connected to the CL-PD67XX CORE_VDD pins. This bit must be set to ‘0’ when the CORE_VDD pins are connect 3.3 volts to preserve TTL-compatible input thresholds to the card socket. ...
Page 62
... Configured for DMA mode on the CL-PD6712 and CL-PD6722. This bit is reserved for the CL-PD6720. On the CL-PD6712 and CL-PD6722, this bit is used to configure system interface signals for nor- mal or DMA operation. At reset, the signals IRQ9, IRQ10, and -VPP_VALID are in non-DMA mode, and this bit is set to ‘ ...
Page 63
... Identification Socket* R:11 a The value for CL-PD6712 is ‘0’, and the value for CL-PD6720 and CL-PD6722 is ‘1’. b This read-only value depends on the revision level of the CL-PD67XX chip. c The value for CL-PD6720 is ‘0’, and the value for CL-PD6712 and CL-PD6722 is ‘1’. ...
Page 64
... This bit has no hardware control function when not in ATA mode. 64 EXTENSION REGISTERS Bit Bit Bit A22 A21 RW:0 RW:0 PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Register Per: socket Register Compatibility Type: ext. Bit Bit Bit 2 1 Speaker Is Scratchpad Bit ATA Mode LED Input RW:0 ...
Page 65
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters 9.6 Extended Index Register Name: Extended Index Index: 2Eh Bit Bit 7 6 This register controls which of the following registers at index 2Fh can be accessed: Register Name at Index 2Fh Scratchpad Data Mask 0 Data Mask 1 Extension Control 1 ...
Page 66
... LED activity disabled. 1 LED activity enabled. This bit allows the LED_OUT* pin to reflect any activity in the card. Whenever PC Card cycles are in process to or from a card in either socket, LED_OUT* will be active (low). Bit 5 — Pull-up Control 0 Pull-ups on CD2, CD1, and VS1#/A_GPSTB and VS2#/B_GPSTB (CL-PD6712) or A_GPSTB and B_GPSTB (CL-PD672X) are in use ...
Page 67
... IOW*). If this interval exceeds the programmed time, the CL-PD6712 or CL-PD6722 assumes that a system write-verify is in progress and generates a dummy DMA write cycle at the PC Card interface. This allows the passing of the DMA acknowledge (and terminal count status) to the card so it can perform any intended verify-cycle functions ...
Page 68
... The maximum DMA acknowledge delay (t2 as shown in Figure 9-2) should be programmed to a time greater than the maximum time required from the system’s issuance of a DMA acknowledge to its issu- ance of a DMA read or write cycle (t1 as shown in Figure 9-2). The t1 time is indicated in the specifications for the systems DMA cycle timing. ...
Page 69
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters 9.7.4 External Data (Socket A, Index 2Fh) Register Name: External Data Index: 2Fh only Bit Bit 7 6 External Data External Data External Data 7 6 RW:0 RW:0 RW:0 Bits 7:0 — External Data This register is updated and accessed according to the setting of bits 3 and 4 of the Socket A Extension Control 2 register (Index 2Fh, Extended Index 0Bh) ...
Page 70
... RW:0 R:0 Function of Socket B External Data Register Bits 7:4 — scratchpad 0 Bits 3:2 — Socket B VS2# and VS1# levels (CL-PD672X only) Bits 1:0 — Socket A VS2# and VS1# levels External read port: B_GPSTB is a read buffer enable for external data on 1 SD[15:8] External write port: B_GPSTB is a write latch enable for SD[15:8] to get 0 latched to an external register ...
Page 71
... VS1#/A_GPSTB (CL-PD6712) or A_GPSTB (CL-PD672X) pins are used to strobe I/O writes on SD[15:8]. Note that setting this bit forces the pull-ups on (CL-PD672X off, independent of the setting of the Pull-Up Control bit (index 2Fh, extended index 03h, bit 5). See Section 9.7.5, Chapter 12, and Chapter 13. Bit 3 — GPSTB on IOR* 0 VS2#/B_GPSTB (CL-PD6712) or B_GPSTB (CL-PD672X) pins (socket B) are used as voltage sense ...
Page 72
... The value representing the number of internal clock cycles for command setup, is then multiplied by the internal clock’s period to determine the command setup time (see Section 15.3.6 for further discussion). ...
Page 73
... RW:00 a Timing set 0 (index 3Bh) resets to 06h for socket timing equal to standard AT-bus-based cycle times. Timing set 1 (3Eh) resets to 0Fh for socket timings equal to standard AT-bus timing using one additional wait state. There are two separate Command Timing registers, each with identical fields. These registers are located ...
Page 74
... The Recovery Timing register for each timing set controls how long a PC Card cycle’s command (that is, -OE, -WE, -IORD, -IOWR; see page 16) recovery will be, in terms of the number of internal clock cycles. The overall command recovery timing length R is programmed by selecting a 2-bit prescaling value (bits ...
Page 75
... CL-PD67XX card socket is operating in ATA mode. Refer to application note AN-PD5, Configuring PCMCIA Sockets for ATA Drive Interface , for more information. All register functions of the CL-PD67XX are available in ATA mode, including socket power control, inter- face signal disabling, and card window control. No memory operations are allowed in ATA mode. ...
Page 76
... -IOIS16 34 Ground a Not supported by the CL-PD67XX. 76 ATA MODE OPERATION (cont.) PC Card Socket Pin ATA Interface Number n/c n/c n/c n/c n -IOIS16 Ground PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters ...
Page 77
... USING GPSTB PINS FOR EXTERNAL PORT CONTROL The CL-PD67XX provides pins that can be programmed to function as general-purpose strobes to exter- nal latches or buffers, allowing them to serve as read ports or write ports mapped into the CL-PD67XX register set. Configuring a GPSTB pin as a read port allows an easy way to read additional card status such as VS1# and VS2# levels, a card socket microswitch status, a card port cover microswitch status, card eject sole- noid position status, or general system signal status ...
Page 78
... GPSTB outputs are totem-pole, their ‘high’ level is driven to the voltage of the ‘+5V’ pin, instead of to high- impedance. If neither bit 3 nor bit 4 is set, the respective GPSTB pin functions as a reserved input in a CL-PD672X VS1# or VS2# input in a CL-PD6712 with an internal pull-up to the ‘+5V’ pin. This internal pull-up is turned off whenever the GPSTB pin is confi ...
Page 79
... On writes, data is written to both the external latch and the internal shadow copy of the External Data register. A read of the respective extended index 0Ah would produce the last value written to the latch. Connection of the ISA bus PWRGOOD signal to the external latch ensures that the latch assumes all ‘0’s at its outputs when the CL-PD67XX is reset. IOR* SD[15:0] (16-bit bus) Figure 12-2. Example GPSTB Read Port (Extension Control 2 bits 4:3 are ‘ ...
Page 80
... Suspend mode). A clock to the CL-PD672X is not required for the external signal at GPSTB to occur, but shadowing of write values in the internal register at Extended Index 0Ah requires that the CL-PD67XX is not in Suspend mode so there is an active internal clock for register writes ...
Page 81
... RW:0 RW:0 On the CL-PD6712, the socket’s VS1# and VS2# pins can be directly connected to the VS1#/GPSTB and VS2#/B_GPSTB pins. No Extension Control 2 register programming is done in this case and the VS1 and VS2 bits appear as bits 0 and 1 of extended register 0Ah at index 6Fh. ...
Page 82
... Socket A VS1 and VS2 to appear as bits 0 and 1, and Socket B VS1 and VS2 to appear as bits 2 and 3): CL-PD672X IOR* IOR* B_GPSTB SD[15:0] SD[15:0] (16-bit bus) Figure 13-2. VS1# and VS2# Sensing on a CL-PD672X (Socket B Extension Control 2 bit 3 is ‘1’) 82 VS1# AND VS2# VOLTAGE DETECTION 5-V Supply VS_RD* +5V † Tristate Buffer (e.g., 1 ’244) † ...
Page 83
... PC Card Standard. 1 Transfer size at socket interface is the same as transfer size on an ISA bus. For 8-bit DMA transfers, connect CL-PD6712 or CL-PD6722 DMA handshake signals to ISA bus DMA channels For 16-bit transfers, connect CL-PD6712 or CL-PD6722 DMA handshake signals to ISA bus DMA channels ...
Page 84
... Terminal counts are passed through to the card from the CL-PD6712 or CL-PD6722 -VPP_VALID pin when bit 6 of the Misc Control 2 register is ‘1’. For a DMA write process, the last-cycle terminal count condition is indicated by -OE being active-low during a card DMA data read cycle. For a DMA read pro- cess, terminal count is indicated by -WE being active-low during the last card cycle. 14.4 Confi ...
Page 85
... Figure 14-2. Card DMA Request and Acknowledge Handshake with Terminal Count Notice that DMA acknowledge to the card as -REG high is only active during the actual DMA read or write card cycle. This means there is no mechanism to deassert DACK to the card: the card must understand that receiving the first DMA cycle is its DMA acknowledgment. ...
Page 86
... At the conclusion of each transfer process, systems send active (high) TC (terminal count) pulses to the -VPP_VALID pin during the last DMA cycles to the CL-PD6712 or CL-PD6722. For a DMA write cycle, TC active is signaled at the socket interface as the -OE pin going low during DMA- type read cycles from the PC Card. ...
Page 87
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters 15. ELECTRICAL SPECIFICATIONS 15.1 Absolute Maximum Ratings Description Ambient temperature under bias Storage temperature Voltage on any pin (with respect to ground) Operating power dissipation Suspend power dissipation Power supply voltage Injection current (latch up) a Stresses above those listed may cause permanent damage to system components. These are stress ratings only ...
Page 88
... PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 Conditions Normal operation CORE_VDD = 3.0 V, Misc Control 2 register, bit 3 is ‘0’ CORE_VDD = 4.5 V, Misc Control 2 register, bit 3 is ‘1’ CORE_VDD = 3.6 V, Misc Control 2 register, bit 3 is ‘0’ CORE_VDD = 5.5 V, Misc Control 2 register, bit 3 is ‘1’ ...
Page 89
... CORE_VDD = 5 2 rated I ISA_VCC V At rated I – 0.5 0 rated ISA_VCC = 3 ISA_VCC = 3 OHC ISA_VCC = 3 pins of the CL-PD67XX. DD ELECTRICAL SPECIFICATIONS , ISA_VCC = 3 ISA_VCC = 3.0 V OHC ISA_VCC – ...
Page 90
... Icc tot(1) operating Power Supply Current, Icc a tot(2) Suspend Power Supply Current, Icc Super Suspend, tot( Clocks a No cards in sockets; or for CL-PD6712 or CL-PD6722, bit 5 of the DMA Control register is a ‘1’. 90 ELECTRICAL SPECIFICATIONS MIN MAX Unit Highest 5 – 0.3 CC 2 ...
Page 91
... ISA–to–PC-Card Host Adapters 15.3 AC Timing Specifications This section includes system timing requirements for the CL-PD67XX. Timings are provided in nanosec- onds (ns), at TTL input levels, with the ambient temperature varying from and V from 3 4.5 to 5.5 V DC. The AT bus speed is 10 MHz unless otherwise noted. Note that an asterisk (*) denotes an active-low signal for the ISA bus interface, and a dash (-) denotes an active-low signal for the PC Card socket interface ...
Page 92
... Except for valid card memory writes, which are zero wait state when internal write FIFO is not full card is removed during a card access cycle, IOCHRDY is three-stated without waiting for end of Command. 5 Based on 25-MHz internal clock, produced either by an internal synthesizer and 14.318-MHz signal applied to CLK pin supplying 25 MHz directly to CLK pin and bypassing the internal synthesizer ...
Page 93
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters ALE t 1a LA[23:17] VALID SA[16:0] SBHE MEMCS16* IOCS16* MEMR*, MEMW* IOR*, IOW* IOCHRDY WRITE DATA READ DATA AEN REFRESH* ZWS* September 1995 PRELIMINARY DATA SHEET v3 VALID ...
Page 94
... Clock active before end of reset 2 t End of PWRGOOD generated reset to first Command 3 1 Clock input must be active for a minimum of 500 ns before PWRGOOD goes active to allow sufficient internal clocks to initialize internal circuitry. PWRGOOD CLK MEMR*, MEMW* IOR*, IOW* 94 ELECTRICAL SPECIFICATIONS ...
Page 95
... Table 15-9. Pulse Mode Interrupt Timing Symbol t IRQ[XX] low or high 1 High-Z IRQ[XX] High-Z = high impedance NOTE: Each time indicated is 2 clock periods of the CLK input to the CL-PD67XX, independent of setting of the Bypass Frequency Synthesizer bit. Figure 15-3. Pulse Mode Interrupt Timing September 1995 PRELIMINARY DATA SHEET v3.0 Parameter t t ...
Page 96
... GPSTB delay after IOR* or IOW* active 1 t GPSTB delay after IOR* or IOW* inactive 2 IOR*, IOW* GPSTB Figure 15-4. General-Purpose Strobe Timing 96 ELECTRICAL SPECIFICATIONS Parameter t 1 PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters MIN MAX Units September 1995 ...
Page 97
... ISA–to–PC-Card Host Adapters 15.3.5 Input Clock Specification Table 15-11.Input Clock Specification Symbol Parameter t CLK pin input rise time 1 t CLK pin input fall time 2 t CLK input low period 3 t CLK input high period 4 V Center voltage at which center period specifi ...
Page 98
... Recovery Timing registers (see Chapter 10 for description of these registers). From this Card cycle’s Setup, Command, and Recovery time for the selected timer set are calcu- lated as follows: Command time = (C Tcp Recovery time = (R Tcp ...
Page 99
... Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns For typical active timing programmed at 280 ns, maximum -WAIT timing is 190 ns after Command active. -REG, -CE[2:1], A[25:0] -OE, -WE -WAIT D[15:0] Write Cycle D[15:0] Read Cycle September 1995 PRELIMINARY DATA SHEET v3.0 Parameter pres ...
Page 100
... Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns For typical active timing programmed at 280 ns, maximum -WAIT timing is 190 ns after Command active. 5 -IOIS16 must go low within 3Tcp + the cycle beginning or -IOIS16 will be ignored and -CE will not be activated. 100 ELECTRICAL SPECIFICATIONS Parameter ...
Page 101
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters -REG, A[25:0] -IOWR, -IORD -WAIT t -IOIS16 -CE1 -CE2 D[15:0] Write Cycle D[15:0] Read Cycle Figure 15-7. Word I/O Read/Write Timing September 1995 PRELIMINARY DATA SHEET v3 ref ELECTRICAL SPECIFICATIONS ...
Page 102
... The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns -REG, A[25:0] -IOWR, -IORD, -OE, -WE -CE1 D[7:0] Write Cycle D[7:0] Read Cycle D[15:8] Read or Write Cycle Figure 15-8. PC Card Read/Write Timing when System Is 8-Bit 102 ELECTRICAL SPECIFICATIONS Parameter pres ...
Page 103
... Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns -REG, A[25:0] t -IOWR, -IORD, -OE, -WE -CE1 -CE2 D[7:0] Write Cycle D[7:0] Read Cycle D[15:8] Read or Write Cycle Figure 15-9. Normal Byte Read/Write Timing (that is., all other byte accesses, including odd I/O September 1995 PRELIMINARY DATA SHEET v3.0 Parameter pres Odd/Even Data Odd/Even Data XX ...
Page 104
... PCMCIA specification for -IOIS16 from A[25:0] change will meet this condition. -REG, A[25:0] t -IOIS16 -CE2 -CE1 -IOWR, -IORD D[7:0] Write Cycle D[7:0] Read Cycle D[15:8] Read or Write Cycle Figure 15-10. 16-Bit System to 8-Bit I/O Card: Odd Byte Timing 104 ELECTRICAL SPECIFICATIONS Parameter pres ...
Page 105
... The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns Based on an internal clock period (25 MHz). September 1995 PRELIMINARY DATA SHEET v3.0 ...
Page 106
... DMA DATA[15:0] to card -VPP_VALID (TC from system) -WE (TC to card) 106 ELECTRICAL SPECIFICATIONS Figure 15-11. DMA Read Cycle Timing PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters September 1995 ...
Page 107
... The Recovery time is determined by the value programmed into the Recovery Timing register, index 3Ch/3Fh. Using the Timer Set 0 default value of 03h, the hold (Recovery) time would be 150 ns Based on an internal clock period (25 MHz). September 1995 PRELIMINARY DATA SHEET v3.0 ...
Page 108
... DMA DATA[15:0] from card 108 ELECTRICAL SPECIFICATIONS Figure 15-12. DMA Write Cycle Timing PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters September 1995 ...
Page 109
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Table 15-19. DMA Request Timing Symbol Parameter t DMA request from socket interface to system 1 1 After FIFO empty, DMA requests held off from being presented to the system until all write data to a card has been emptied from the socket interface FIFO ...
Page 110
... Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. 110 PACKAGE SPECIFICATIONS 21.60 (0.850) 22.40 (0.882) 19.90 (0.783) 20.10 (0.791) 0.10 (0.004) 0.30 (0.012) CL-PD6712 144-Pin VQFP Pin 1 Indicator 17.50 (0.689) REF PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters 19.90 (0.783) 20.10 (0.791) 17.50 (0.689) REF 1.00 (0.039) 1.25 (0.049) REF 1.50 (0.059) 0 MIN 7 MAX ...
Page 111
... Drawing above does not reflect exact package pin count. 3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. September 1995 PRELIMINARY DATA SHEET v3.0 30.35 (1.195) 30.85 (1.215) 27.90 (1.098) 28.10 (1.106) 0.13 (0.005) 0.28 (0.011) CL-PD6720 or CL-PD6722 208-Pin PQFP Pin 1 Indicator 25.50 (1.004) REF 3.17 (0.125) 0.40 (0.016) 3.67 (0.144) 0.75 (0.030) 27 ...
Page 112
... Drawing above does not reflect exact package pin count. 3) Before beginning any new design with this device, please contact Cirrus Logic for the latest package information. 112 PACKAGE SPECIFICATIONS 29.60 (1.165) 30.40 (1.197) 27.80 (1.094) 28.20 (1.110) 0.17 (0.007) 0.27 (0.011) CL-PD6720 or CL-PD6722 208-Pin VQFP Pin 1 Indicator 1.35 (0.053) 0.45 (0.018) 1.45 (0.057) 0.75 (0.030) PRELIMINARY DATA SHEET v3.0 CL-PD6712/’ ...
Page 113
... Product Line: Portable Products Part Number † Contact Cirrus Logic for up-to-date information on revisions. September 1995 PRELIMINARY DATA SHEET v3.0 † Revision Temperature Range Commercial Package Type Plastic Quad Flat Pack (CL-PD6720 and CL-PD6722 Very-tight-pitch Quad Flat Pack ORDERING INFORMATION EXAMPLE 113 ...
Page 114
... Using the Cirrus Logic BBS Cirrus Logic maintains a BBS (bulletin board system) 24 hours a day for customers to obtain up-to-date files and information. For the CL-PD67XX, the BBS gives access to utilities, schematics, and software upgrades. Cirrus Logic strictly controls access to this BBS. All downloadable files are checked by Cirrus Logic and customers cannot upload fi ...
Page 115
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Using the FTP Server In addition to the BBS, Cirrus Logic maintains an anonymous FTP site on the internet. The address is ftp.cirrus.com. Using any password, you can log on as anonymous or FTP. You can also access this site using a World-Wide Web browser by linking from the Cirrus Logic home page at the address http://www ...
Page 116
... Bit RDY WP -CD2 Write Protect Card Detect PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Register Per: chip Register Compatibility Type: 365 Bit Bit 2 1 Register Per: chip Register Compatibility Type: 365 Bit Bit 2 1 ...
Page 117
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters a Bit 7 is the inversion of the value of the -VPP_VALID pin (see page 15). b Bit 5 is the value of the RDY/-IREQ pin (see page 17). c Bit 4 is the value of the WP/-IOIS16 pin (see page 17). ...
Page 118
... Start Address 15:8 RW:00000000 Bit Bit Bit End Address 7:0 RW:00000000 PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Register Per: socket Register Compatibility Type: 365 Bit Bit Bit 2 1 Memory Map 2 Memory Map 1 Memory Map 0 Enable ...
Page 119
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Register Name: System I/O Map 0–1 End Address High Index: 0Bh, 0Fh Bit Bit 7 6 Register Name: Card I/O Map 0–1 Offset Address Low Index: 36h, 38h Bit Bit This bit must be programmed to ‘0’. ...
Page 120
... Offset Address 19:12 RW:00000000 Bit Bit Bit Offset Address 25:20 RW:000000 PRELIMINARY DATA SHEET v3.0 CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Register Per: socket Register Compatibility Type: 365 Bit Bit Bit Register Per: socket Register Compatibility Type: 365 Bit ...
Page 121
... The value for CL-PD6712 is ‘0’, and the value for CL-PD6720 and CL-PD6722 is ‘1’. b This read-only value depends on the revision level of the CL-PD67XX chip. c The value for CL-PD6720 is ‘0’, and the value for CL-PD6712 and CL-PD6722 is ‘1’. Register Name: ATA Control Index: 26h Bit ...
Page 122
... Register Compatibility Type: ext. Bit Bit Bit 2 1 Register Per: socket Register Compatibility Type: ext. Bit Bit Bit 2 1 Register Per: socket Register Compatibility Type: ext. Bit Bit Bit Power LED Activity Auto Power CC Enable Clear Disable Lock RW:0 RW:0 RW:0 September 1995 ...
Page 123
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters Register Name: Maximum DMA Acknowledge Delay Index: 2Fh Bit Bit 7 6 Register Name: External Data Index: 2Fh Bit Bit 7 6 External Data External Data External Data 7 6 RW:0 RW:0 RW:0 Register Name: External Data Index: 6Fh ...
Page 124
... Command Prescalar Select RW:00 a Timing set 0 (index 3Bh) resets to 06h for socket timing equal to standard AT-bus-based cycle times. Timing set 1 (3Eh) resets to 0Fh for socket timings equal to standard AT-bus timing using one additional wait state. Register Name: Recovery Timing 0–1 Index: 3Ch, 3Fh ...
Page 125
... AEN 13 ALE 12 ATA Control register 64 ATA mode description 75 overview 29 pin cross reference 75 ATA Mode bit 64 Auto Power Clear Disable bit 66 Auto-Power bit 41 Auto-Size I/O Window 0 bit 49 Auto-Size I/O Window 1 bit pin name 16 See also the pin name B_GPSTB 19 Battery Dead Or Status Change bit 44 ...
Page 126
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters DMA System bit 62 Drive LED Enable bit 61 Dual/Single Socket* bit 63 E Empty Write FIFO bit 60 Enable Manage Int bit 42 End Address 15:8 bits 51 End Address 19:12 bits 55 End Address 23:20 bits 55 End Address 7:0 bits 51 Extended Data register 65 ...
Page 127
... REG Setting bit 57 Register Index bits 33 RESET 18 Revision bits 37 -RI 18 RI_OUT* 14 Ring Indicate Enable bit 43 126 INDEX CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters S SA[16:0] 12 SBHE* 12 SD[15:0] 12 Setup Multiplier Value bits 72 Setup Prescalar Select bit 72 Setup Timing 0–1 registers 72 SLOT_VCC ...
Page 128
... CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters VDD. See CORE_VDD 20 – voltage sense 81 82 overview 27 V Valid bit 39 PP VPP_PGM 20 -VPP_VALID 15 VPP_VCC Power bits 41 PP VS1#/A_GPSTB 19 VS2#/B_GPSTB 19 W -WAIT 18 -WE 17 Window Data Size bit 54 windowing 22 WP/-IOIS16 17 ...
Page 129
... INDEX CL-PD6712/’20/’22 ISA–to–PC-Card Host Adapters September 1995 PRELIMINARY DATA SHEET v3.0 ...
Page 130
... Cirrus Logic, Inc. Cirrus, Cirrus Logic, AccuPak, Alpine, Clear3D, Crystal, CrystalClear, CrystalClear Imaging, CrystalWare, DirectVPM, DIVA, FastEn, FastPath, FeatureChips, FilterJet, Get into it, Good Data, IntelliFilter, Laguna, ...