ia82527 Innovasic Semiconductor Inc., ia82527 Datasheet - Page 40

• Manufacturer Part Number: ia82527
• Description: Serial Communications Controller?can Protocol
• Manufacturer: Innovasic Semiconductor Inc.

IA82527
CAN Serial Communications Controller
Table 12. Mode 3: Asynchronous Operation Timing
a
edge of cs_n for the write and the falling edge of cs_n for the read are separated by at least 2
b
edge of cs_n for the first write and the rising edge of cs_n for the second write are separated by at least
2
A ―Read Cycle without Previous Write‖ is where a read cycle follows a write cycle and where the rising
A ―Write Cycle with a Previous Write‖ is a write cycle following a previous write cycle where the rising
Symbol
1/t
1/t
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
AVCL
CLDV
KLDV
CHDV
CHDH
CHDZ
CHKH 1
CHKH 2
CHKZ
CHCL
CHAI
CHRI
CLCH
DVCH
CLKL
CHKL
COPD
CHCL
t
XTAL
SCLK
MCLK
MCLK
.
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address or r-w_n Valid to cs_n Low Setup
cs_n Low to Data Valid (for High-Speed Registers 02H, 04H,
and 05H)
cs_n Low to Data Valid (for Low-Speed Registers) Read
Cycle without Previous Write
cs_n Low to Data Valid (for Low-Speed Registers) Read
Cycle with Previous Write
dsack0_n Low to Output Data Valid (for High-Speed Read
Registers)
dsack0_n Low to Output Data Valid (for Low-Speed Read
Registers)
Input Data Hold after cs_n High
Output Data Hold after cs_n High
cs_n High to Output Data Float
cs_n High to dsack0_n = 2.4V (an on-chip pull-up will drive
dsack0_n to approximately 2.4V; an external pull-up is
required to drive this signal to a higher voltage)
cs_n High to dsack0_n = 2.8V
cs_n High to dsack0_n Float
cs_n Width between Successive Cycles
cs_n High to Address Invalid
cs_n High to r-w_n Invalid
cs_n Width Low
CPU Write Data Valid to cs_n High
cs_n Low to dsack0_n Low (for High- and Low-Speed
Registers) Write Cycle without Previous Write
End of Previous Write (cs_n High) to dsack0_n Low for a
Write Cycle with a Previous Write
clkout Period (CD
Register representing the clkout divisor)
clkout High Period (CD
Register representing the clkout divisor)
V
is the value loaded in the CLKOUT
V
is the value loaded in the CLKOUT
Parameter
a
b
IA211080504-02
Page 40 of 53
(CD
(CD
½ t
Minimum
OSC
8 MHz
4 MHz
2 MHz
15 ns
25 ns
65 ns
20 ns
V
V
3 ns
0 ns
0 ns
0 ns
0 ns
0 ns
0 ns
0 ns
7 ns
5 ns
0 ns
0 ns
+ 1)
+ 1)
–
–
–
– 10
http://www.Innovasic.com
t
OSC
March 12, 2009
Customer Support:
(CD
t
OSC
2 t
1.5 t
3.5 t
Maximum
Data Sheet
[phone]
16 MHz
10 MHz
MCLK
100 ns
100 ns
150 ns
100 ns
8 MHz
V
t
55 ns
23 ns
35 ns
55 ns
67 ns
– 15
MCLK
+ 1)
ns
MCLK
MCLK
–
–
–
–
–
–
–
–
–
+ 145
.
+
+
½