ia82527 Innovasic Semiconductor Inc., ia82527 Datasheet - Page 34

• Manufacturer Part Number: ia82527
• Description: Serial Communications Controller?can Protocol
• Manufacturer: Innovasic Semiconductor Inc.

IA82527
CAN Serial Communications Controller
Table 10. Mode 0 and Mode 1: General Bus and Ready Timing
a
than 2 t
b
than 2 t
A ―Read Cycle without a Previous Write‖ is where a read cycle follows a write cycle and there is greater
A ―Previous Write Cycle is Active‖ is where the rising edge of wr_n or wrh_n for the second write is less
1/t
1/t
1/t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
HYZ
t
t
t
t
t
Symbol
AVLL
LLAX
LHLL
LLRL
CLLL
QVWH
WHQX
WLWH
WHLH
WHCH
RLRH
RLDV
RLDV1
RLDV1
RHDZ
CLYV
WLYZ
RLYZ
RLYZ
WHDV
COPO
CHCL
XTAL
SCLK
MCLK
MCLK
MCLK
Oscillator Frequency
System Clock Frequency
Memory Clock Frequency
Address Valid to ale Low
Address Hold after ale Low
ale High Time
ale Low to rd_n Low
cs_n Low to ale Low
Data Setup to wr_n or wrh_n High
Input Data Hold after wr_n or wrh_n High
wr_n or wrh_n Pulse Width
wr_n or wrh_n High to Next ale High
wr_n or wrh_n High to cs_n High
rd_n Pulse Width. This time is long enough to initiate a double
read cycle by loading the High Speed Registers (04H, 05H), but is
too short to read from 04H and 05H (see t
rd_n Low to Data Valid (only for Registers 02H, 04H, 05H)
rd_n Low Data to Data Valid (for all Registers except 02H, 04H,
05H) for Read Cycle without a Previous Write
rd_n Low Data to Data Valid (for all Registers except 02H, 04H,
05H) for Read Cycle with a Previous Write
Data Float after rd_n High
cs_n Low to ready Setup (Load Capacitance on the ready Output
= 50 pF, V
cs_n Low to ready Setup (Load Capacitance on the ready Output
= 50 pF, V
wr_n or wrh_n Low to ready Float for a Write Cycle if No Previous
Write is Pending
End of Last Write to ready Float for a Write Cycle if a Previous
Write Cycle is Active
rd_n Low to ready Float (for all registers except 02H, 04H, 05H)
for Read Cycle without a Previous Write
rd_n Low to ready Float (for all registers except 02H, 04H, 05H)
for Read Cycle with a Previous Write
wr_n or wrh_n High to Output Data Valid on Port 1 or Port 2
clkout Period (CD
representing the clkout divisor)
clkout High Period (CD
Register representing the clkout divisor)
between the rising edge of wr_n or wrh_n and the falling edge of rd_n.
after the rising edge of wr_n or wrh_for the first write.
OL
OL
= 1.0 V)
= 0.45 V)
V
is the value loaded in the CLKOUT Register
b
V
is the value loaded in the CLKOUT
Parameter
IA211080504-02
Page 34 of 53
a
RLDV
a
).
(CD
(CD
½ t
Minimum
8 MHz
4 MHz
2 MHz
7.5 ns
10 ns
30 ns
20 ns
10 ns
27 ns
10 ns
30 ns
40 ns
OSC
t
8 ns
0 ns
0 ns
0 ns
t
MCLK
V
V
OSC
http://www.Innovasic.com
–
–
–
–
–
–
–
–
+ 1)
+ 1)
– 10
March 12, 2009
Customer Support:
(CD
½ t
Data Sheet
1.5 t
3.5 t
[phone]
Maximum
2 t
2 t
4 t
2 t
16 MHz
10 MHz
100 ns
100 ns
145 ns
100 ns
100 ns
100 ns
500 ns
8 MHz
55 ns
45 ns
32 ns
40 ns
OSC
MCLK
MCLK
MCLK
MCLK
V
MCLK
MCLK
–
–
–
–
–
–
–
–
–
–
–
–
+ 1)
– 15
+
+
+
+
+
+