act7006 Aeroflex Circuit Technology, act7006 Datasheet - Page 13

• Manufacturer Part Number: act7006
• Description: Act7005/7006 Single Package Solution Dual Transceiver, Protocol, Subsystem
• Manufacturer: Aeroflex Circuit Technology

Aeroflex Circuit Technology
Name
INT #1
GOOD BLOCK (RT)
VALID (BC)
INT #2
VALID TRANS (RT)
INVALID (BC)
SYNC NO DATA
SYNC W/DATA
DONE
BUFF EF
MODERESET
Table 6 – Discrete Interrupts Summary
Use
Indicates reception of a valid block of data. The RECEIVE COMMAND WORD
is loaded in RCV CMD WD Register. This interrupt is issued after the new
block of data is moved into the Internal RAM.
Indicates that the Bus Controller has initiated and observed a valid message
transfer on the 1553 data bus.
Indicates reception of a valid TRANSMIT COMMAND WORD. The
TRANSMIT COMMAND WORD is loaded in CMD WD Register. Note: This
interrupt does not necessarily indicate that the transmitted data was received
by the bus controller.
Indicates that the Bus Controller has initiated a message transfer on the data
bus, but the message traffic has been deemed invalid.
Indicates reception of a valid mode command SYNCHRONIZE WITHOUT
DATA
Indicates reception of a valid mode command SYNCHRONIZE WITH DATA.
The synchronize data word is loaded into the SYNC/STAT WD #2/RMD
REGISTER. This interrupt will not be issued if a word count high or low error
occurs.
This interrupt is issued in response to an I/0 command from the subsystem. In
response to an I/0 load OUTPUT buffer command, it indicates that the
complete 32 word message block (SUBADDRESS) has been loaded into the
OUTPUT FIFO buffer. In response to an I/0 load internal RAM from INPUT
FIFO buffer command, it indicates the full message (1 to 32 WORDS) has
been loaded.
TIMING
*NOTE:
In the unusual case where a superceding transmit command on the redundant
bus occurs at the returned status time for a valid 32 word receive,
simultaneously with an I/0 transfer request, the DONE interrupt may be
delayed for an additional 16.5 usec.
This flag may be used to speed up read data operation in response to an I/0
load OUTPUT FIFO buffer command. The BUFF EF flag will go high when the
first word is loaded into the OUTPUT FIFO buffer. The word may be read at
that time. Please see Figure 6.
Indicates reception of a valid RESET mode command.
a. In response to an I/0 load OUTPUT buffer: 16.5 to 33 µsec.*
b. In response to an I/0 load RAM from INPUT buffer: 16.5 to 33 µsec for 32
WORDS*, for SHORTER LOAD OPERATIONS SUBTRACT 0.5 µsec per
(16 bit) word, i.e., 17 µsec to 0.5 µsec for single word.
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SCD7005 REV B 8/2/01
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