lc7152 Sanyo Semiconductor Corporation, lc7152 Datasheet - Page 8

• Manufacturer Part Number: lc7152
• Description: Universal Dual-pll Frequency Synthesizers
• Manufacturer: Sanyo Semiconductor Corporation

Description of Serial Data
No.
(1)
(2)
(3)
(4)
(5)
(6)
(7)
Side-A
programmable
divider data: DA0
to DA15
Side-B
programmable
divider data: DB0
to DB15
Reference
frequency data: R0
to R13
Output port data:
OA, OB
Input frequency
range switching
data: FA, FB
Standby mode data
: SB
Unlock detection
data
: UL0, UL1
: UE0, UE1
Controller/Data
.
.
.
.
.
.
.
.
.
.
.
.
This data sets the side-A programmable divider number. This data is a
binary value in which DA0 is the LSB.
The range of divider values that can be set is 272 to 65,535.
This data sets the side-B programmable divider number. This data is a
binary value in which DB0 is the LSB.
The range of divider values that can be set is 272 to 65,535.
This data sets the reference divider number. This data is a binary value in
which R0 is the LSB.
The range of divider values that can be set is 8 to 16,383.
This data determines the output on the general-purpose output port.
Data 0: open; Data 1: low
During the power-on reset in the LC7152NM, OA and OB are both ‘‘0’’.
This data switches the input frequency range for the PIA and PIB pins.
(FA
In the case of the LC7152KM: Data 1: 55 to 80 MHz (V
This data puts the PLL in standby mode.
During the power-on reset in the LC7152NM, SB is ‘‘1’’.
This is the phase error detection threshold data that is used for PLL
lock/unlock discrimination. If the threshold shown in the table is exceeded,
the unlocked state is detected.
The detected phase error (øE) signal can be extended by a certain amount
of time and output on the LDA and LDB pins. This data determines the
length of this extension. However, when UL0 = UL1 = 0, the phase error is
not extended, and is output directly.
(Note) Note that if the data changes in lock state, the PLL will be unlocked
UL0 UL1
UE0
0
1
0
1
.
.
0
1
0
1
NA = fVCO-A/fref
NB = fVCO-B/fref
(reference frequency: fref) = (f
OA
OB
SB = 1: standby mode (LDB pin: open)
SB = 0: standby mode off
LC7152, 7152M, 7152NM, 7152KM
(Actual divider number) = (setting) x 2
PIA, FB
temporarily.
0
0
1
1
UE1
0
0
1
1
Single PLL operation: Side-A operating, side-B stopped
Dual PLL operation: Side-A operating, side-B operating
OUTA
OUTB
Phase error
Data
threshold
[0]
[1]
detector
16/f
64/f
4/f
32
64
Reference
4
8
frequency
0
X’tal
PIB)
X’tal
X’tal
fref
(1/fref)
(1/fref)
(1/fref)
(1/fref)
Supply voltage (V
16.00
4.0
1.00
4.00
1.5 to 23 MHz
20 to 55 MHz
2.0 to 3.3 V
Description
1 kHz
32.0
64.0
X’tal
4.0*
8.0
XIN : fXIN [MHz] example
Reference frequency :
: XIN)/(actual divider number)
7.2
0.55
2.22
8.88
fref [kHz] example
DD
5 kHz
12.8
6.4*
0.8
1.6
)
0.50
2.00
8.00
8.0
(*standard value)
DD
12.5 kHz
10.24
unit : ms
5.12*
0.39
1.56
6.25
0.32
0.64
2.56
= 2.7 V to 3.3 V)
unit : µs
12.8
0.31
1.20
5.00
Continued on next page.
R0 to R13
R0 to R13
UL0 Ul1 UE0 UE1
DA0 to DA15
DB0 to DB15
Related Data
No.3889-8/13