D485505G NEC [NEC], D485505G Datasheet - Page 5

• Manufacturer Part Number: D485505G
• Description: LINE BUFFER 5K-WORD BY 8-BIT
• Manufacturer: NEC [NEC]

2. Operation Mode
2.1 Write Cycle
input.
line (5,048 bits) delay and write data can be processed with the same clock. Refer to Write Cycle Timing Chart.
the WCK rising edge is in the WE = “H” level (t
at this time.
incrementing again.
2.2 Read Cycle
and data is output after t
the RCK rising edge is in the RE = “H” level (t
this time.
2.3 Write Reset Cycle/Read Reset Cycle
address pointers are not defined at that time.
RCK, and then input the RSTW and RSTR signals to initialize the circuit.
Reset Cycle Timing Chart, Read Reset Cycle Timing Chart.
Remark Write and read reset cycles can be executed at any time and do not depend on the state of RE or WE.
For this reason, setup time and hold time are specified for the rising edge of the clock (RCK, WCK).
When the WE input is enabled (“L” level), a write cycle is executed in synchronization with the WCK clock
The data inputs are strobed by the rising edge of the clock at the end of a cycle so that read data after a one-
When WE is disabled (“H” level) in a write cycle, the write operation is not performed during the cycle which
Unless inhibited by WE, the internal write address will automatically wrap around from 5,047 to 0 and begin
When the RE input is enabled (“L” level), a read cycle is executed in synchronization with the RCK clock input
When RE is disabled (“H” level) in a read cycle, the read operation is not performed during the cycle which
After power up, the PD485505 requires the initialization of internal circuits because the read and write
It is necessary to satisfy setup requirements and hold times as measured from the rising edge of WCK and
Write and read reset cycles can be executed at any time and the address pointer returns zero. Refer to Write
PD485505 is a synchronous memory. All signals are strobed at the rising edge of the clock (RCK, WCK).
AC
. Refer to Read Cycle Timing Chart.
Data Sheet M10059EJ7V0DS00
REW
WEW
). The RCK does not increment the read address pointer at
). The WCK does not increment the write address pointer
PD485505
5