D485505G NEC [NEC], D485505G Datasheet - Page 13

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D485505G

Manufacturer Part Number
D485505G
Description
LINE BUFFER 5K-WORD BY 8-BIT
Manufacturer
NEC [NEC]
Datasheet

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Quantity
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Manufacturer:
NEC
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4. Application
4.1 1 H Delay Line
WCK/RCK
Data Input
(Output)
RSTW /
Remark RE, WE = “L” level
(Input)
(Input)
(Input)
PD485505 easily allows a 1 H (5,048 bits) delay line (see Figure 4.1).
RSTR
Write
Read
D
D
OUT
IN
8
t
RS
t
t
WCW
RCW
Cycle 0
t
t
t
WCK
RCK
RH
t
t
t
DS
WCP
RCP
40 MHz Clock
(0)
t
DH
Cycle 1
Figure 4.2 1 H Delay Line Timing Chart
(5,048 Cycles)
(1)
Figure 4.1 1 H Delay Line Circuit
WCK
D
WE
Cycle 2
IN
1 H
RSTW
Data Sheet M10059EJ7V0DS00
(2)
(5,046)
Cycle 5,047
RSTR
(5,047)
RCK
D
Cycle 0’
Cycle 0
RE
OUT
t
AC
t
DS
(0’)
(0)
t
t
DH
OH
Cycle 1’
Cycle 1
(5,048 Cycles)
Reset
(1’)
2 H
(1)
Cycle 2’
Cycle 2
8
PD485505
(2’)
Data Output
Cycle 3’
Cycle 3
(2)
13
(3’)
(3)

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