km6161002a Samsung Semiconductor, Inc., km6161002a Datasheet - Page 2

• Manufacturer Part Number: km6161002a
• Description: 64kx16 Bit High Speed Static Ram 5v Operating , Revolutionary Pin Out. Operated At Commercial And Industrial Temperature Range.
• Manufacturer: Samsung Semiconductor, Inc.

KM6161002A, KM6161002AI
• Fast Access Time 12, 15, 20ns(Max.)
• Low Power Dissipation
• Single 5.0V 10% Power Supply
• TTL Compatible Inputs and Outputs
• I/O Compatible with 3.3V Device
• Fully Static Operation
• Three State Outputs
• Center Power/Ground Pin Configuration
• Data Byte Control : LB:I/O
• Standard Pin Configuration
ORDERING INFORMATION
FUNCTIONAL BLOCK DIAGRAM
FEATURES
64K x 16 Bit High-Speed CMOS Static RAM
A
A
A
A
A
A
A
A
A
WE
OE
UB
LB
CS
Operating KM6161002A - 12 : 190mA(Max.)
- No Clock or Refresh required
KM6161002A -12/15/20
KM6161002AI -12/15/20
1
2
3
4
5
6
7
8
9
Standby (TTL)
I/O
I/O
1
9
~I/O
~I/O
8
16
(CMOS) : 8mA(Max.)
KM6161002A - 15 : 185mA(Max.)
KM6161002A - 20 : 180mA(Max.)
KM6161002AJ : 44-SOJ-400
KM6161002AT : 44-TSOP2-400F
Clk Gen.
: 25mA(Max.)
Cont.
Cont.
Data
Data
Gen.
CLK
1
~I/O
A
0
8,
A
UB:I/O
Commercial Temp.
Industrial Temp.
Pre-Charge Circuit
10
128x16 Columns
Column Select
Memory Array
I/O Circuit &
A
512 Rows
11
9
~I/O
A
12
16
A
13
A
14
A
15
- 2 -
GENERAL DESCRIPTION
The KM6161002A is a 1,048,576-bit high-speed Static Random
Access Memory organized as 65,536 words by 16 bits. The
KM6161002A uses 16 common input and output lines and has
an output enable pin which operates faster than address access
time at read cycle. Also it allows that lower and upper byte
access by data byte control(UB, LB). The device is fabricated
using SAMSUNG s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
KM6161002A is packaged in a 400mil 44-pin plastic SOJ or
TSOP2 forward.
PIN FUNCTION
PIN CONFIGURATION
I/O
Pin Name
A
1
0
WE
V
V
N.C
CS
OE
UB
LB
~ I/O
- A
CC
SS
N.C.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Vcc
Vss
WE
15
CS
A
A
A
A
A
A
A
A
A
16
0
1
2
3
4
1
2
3
4
5
6
7
8
5
6
7
8
10
11
12
13
14
15
16
17
18
19
20
21
22
1
2
3
4
5
6
7
8
9
Address Inputs
Write Enable
Chip Select
Output Enable
Lower-byte Control(I/O
Upper-byte Control(I/O
Data Inputs/Outputs
Power(+5.0V)
Ground
No Connection
TSOP2
SOJ/
Pin Function
(Top View)
CMOS SRAM
PRELIMINARY
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
1
9
~I/O
~I/O
February 1998
A
A
A
OE
UB
LB
I/O
I/O
I/O
I/O
Vss
Vcc
I/O
I/O
I/O
I/O
N.C.
A
A
A
A
N.C.
15
14
13
12
11
10
9
16
15
14
13
12
11
10
9
8
16
)
)
Rev 4.0