km6161002a Samsung Semiconductor, Inc., km6161002a Datasheet
km6161002a
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km6161002a Summary of contents
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... Rev. 3.0 Add Industrial Temperature Range parts 3.1. Add Industrial Temperature Range parts with the same parame- ters as Commercial Temperature Range parts. 3.1.1. Add KM6161002AI parts for Industrial Temperature Range. 3.1.2. Add ordering information. 3.1.3. Add the condition for operating at Industrial Temp. Range. 3.2. Add the test condition for Voh1 with Vcc= ...
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... The KM6161002A is a 1,048,576-bit high-speed Static Random Access Memory organized as 65,536 words by 16 bits. The KM6161002A uses 16 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. Also it allows that lower and upper byte access by data byte control(UB, LB) ...
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... KM6161002A, KM6161002AI ABSOLUTE MAXIMUM RATINGS* Parameter Voltage on Any Pin Relative Voltage on V Supply Relative Power Dissipation Storage Temperature Operating Temperature Commercial Industrial * Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied ...
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... KM6161002A, KM6161002AI AC CHARACTERISTICS ( TEST CONDITIONS Parameter Input Pulse Levels Input Rise and Fall Times Input and Output timing Reference Levels Output Loads NOTE: The above test conditions are also applied at industrial temperature range Output Loads(A) D OUT 255 READ CYCLE ...
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... KM6161002A, KM6161002AI WRITE CYCLE Parameter Symbol Write Cycle Time Chip Select to End of Write Address Set-up Time Address Valid to End of Write Write Pulse Width(OE High) Write Pulse Width(OE Low) UB, LB Valid to End of Write Write Recovery Time Write to Output High-Z Data to Write Time Overlap ...
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... KM6161002A, KM6161002AI TIMING WAVEFORM OF READ CYCLE(2) Address CS UB Data out High-Z NOTES(READCYCLE high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address and t are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V ...
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... KM6161002A, KM6161002AI TIMING WAVEFORM OF WRITE CYCLE(2) Address CS UB Data in Data out TIMING WAVEFORM OF WRITE CYCLE(3) Address CS UB High-Z Data in High-Z Data out (OE =Low fixed CW( WP1(2) AS( High-Z Valid Data t WHZ(6) High-Z (CS=Controlled CW( ...
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... KM6161002A, KM6161002AI TIMING WAVEFORM OF WRITE CYCLE(4) Address CS UB High-Z Data in High-Z Data out NOTES(WRITE CYCLE) 1. All write cycle timing is referenced from the last valid address to the first transition address write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE going low ...
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... KM6161002A, KM6161002AI PACKAGE DIMENSIONS 44-SOJ-400 #44 11.18 0.12 0.440 0.005 #1 +0.10 0.43 -0.05 +0.004 0.017 0. -0.002 0.0375 44-TSOP2-400F #44 #1 18.81 MAX. 0.741 18.41 0.10 0.725 0.004 0.35 0.805 0. 0.032 0.014 0.004 28.98 MAX 1.141 25.58 0.12 1.125 0.005 +0.10 0.71 -0.05 1.27 +0.004 0.028 0.050 -0.002 #23 11.76 0.20 0.463 0.008 #22 1.00 1.20 0.10 MAX. 0.039 0.047 0.004 0.05 MIN. 0.80 0.002 0.0315 - 9 - PRELIMINARY CMOS SRAM ...