k4d553238f-jc Samsung Semiconductor, Inc., k4d553238f-jc Datasheet - Page 5

• Manufacturer Part Number: k4d553238f-jc
• Description: 256mbit Gddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

INPUT/OUTPUT FUNCTIONAL DESCRIPTION
*1 : The timing reference point for the differential clocking is the cross point of CK and CK.
K4D553238F-JC
DQS
For any applications using the single ended clocking, apply V
DQ
DM
V
CK, CK*1
BA
V
A
DDQ
NC/RFU
0
DD
Symbol
0
V
MCL
CKE
RAS
CAS
0
0
WE
CS
0
~ DQ
~ A
REF
~ DQS
~ DM
, BA
/V
/V
SS
SSQ
11
1
31
3
3
Input/Output
Input
Input
Input
Input
Input
Input
Input
Input/Output
Input
Input
Power Supply
Power Supply
Power Supply
No connection/
Reserved for future use
Must Connect Low
Type
The differential system clock Input.
All of the inputs are sampled on the rising edge of the clock except
DQ
Activates the CK signal when high and deactivates the CK signal
when low. By deactivating the clock, CKE low indicates the Power
down mode or Self refresh mode.
CS enables the command decoder when low and disabled the com-
mand decoder when high. When the command decoder is disabled,
new commands are ignored but previous operations continue.
Latches row addresses on the positive going edge of the CK with
RAS low. Enables row access & precharge.
Latches column addresses on the positive going edge of the CK with
CAS low. Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Data input and output are synchronized with both edge of DQS.
DQS
DQS
Data In mask. Data In is masked by DM Latency=0 when DM is high
in burst write. DM
DQ
Data inputs/Outputs are multiplexed on the same pins.
Selects which bank is to be active.
Row/Column addresses are multiplexed on the same pins.
Row addresses : RA
Column address CA
Power and ground for the input buffers and core logic.
Isolated power supply and ground for the output buffers to provide
improved noise immunity.
Reference voltage for inputs, used for SSTL interface.
This pin is recommended to be left "No connection" on the device
Must connect low
’
16
s and DM
0
3
~ DQ
- 5 -
for DQ
REF
for DQ
to CK pin.
23,
0
24
’
s that are sampled on both edges of the DQS.
DM
~ DQ
~ DQ
0
3
for DQ
for DQ
7,
8
0
31.
DQS
is used for auto precharge.
~ RA
0
24
1
11
~ DQ
for DQ
~ DQ
, Column addresses : CA
Function
7,
31.
256M GDDR SDRAM
8
DM
~ DQ
1
for DQ
15,
DQS
Rev 1.0 (Mar. 2004)
8
~ DQ
2
for DQ
15,
0
~ CA
DM
16
2
~ DQ
7
for
,CA
23,
9