k4d553238f-jc Samsung Semiconductor, Inc., k4d553238f-jc Datasheet - Page 14

• Manufacturer Part Number: k4d553238f-jc
• Description: 256mbit Gddr Sdram
• Manufacturer: Samsung Semiconductor, Inc.

tQH Timing (CL4, BL2)
Note 1 :
- A new AC timing term, tQH which stands for data output hold time from DQS is difined to account for clock duty cycle
- tQHmin = tHP-X where
- The previously used definition of tDV(=0.35tCK) artificially penalizes system timing budgets by assuming the worst case
- The JEDEC GDDR specification currently defines the output data valid window(tDV) as the time period when the data
COMMAND
K4D553238F-JC
variation and replaces tDV
. tHP=Minimum half clock period for any given cycle and is defined by clock high or clock low time(tCH,tCL)
. X=A frequency dependent timing allowance account for tDQSQmax
strobe and all data associated with that data strobe are coincidentally valid.
output vaild window even then the clock duty cycle applied to the device is better than 45/55%
CK, CK
DQS
DQ
CS
READA
0
1
1
2
- 14 -
3
tDQSQ(max)
4
Qa0
tQH
tHP
256M GDDR SDRAM
tDQSQ(max)
Qa1
Rev 1.0 (Mar. 2004)
5