hd66789 Renesas Electronics Corporation., hd66789 Datasheet
hd66789
Related parts for hd66789
hd66789 Summary of contents
Page 1
... HD66789 528-channel, One-chip Driver for Amorphous TFT Panels with 262,144-color display RAM, Power Supply Circuit, and Gate Circuit Description ......................................................................................................... 5 Features ......................................................................................................... 6 Block Diagram .................................................................................................... 7 Pin Functions ...................................................................................................... 8 PAD arrangement................................................................................................ 14 PAD Coordinate.................................................................................................. 15 BUMP Arrangements.......................................................................................... 17 Block Function.................................................................................................... 18 1. System Interface ............................................................................................................... 18 2. External Display Interface ................................................................................................ 19 3. Bit Operations ................................................................................................................... 19 4 ...
Page 2
... HD66789 Display Control 1 (R07h)....................................................................................................... 36 Display Control 2 (R08h)....................................................................................................... 38 Display control 3 (R09h) ....................................................................................................... 40 Frame Cycle Control (R0Bh)................................................................................................. 41 External Display Interface Control (R0Ch) ........................................................................... 44 Power Control 1 (R10h) Power Control 2 (R11h) ................................................................. 48 Power Control 3 (R12h) Power Control 4 (R13h) ................................................................. 51 RAM Address Set (R21h)...................................................................................................... 53 Write Data to GRAM (R22h)................................................................................................. 54 RAM Access through RGB-I/F and System I/F..................................................................... 59 Read Data Read from GRAM (R22h) ...
Page 3
... Relationship between RAM data and output level................................................................. 121 8-color Display Mode ......................................................................................... 122 System Configuration ......................................................................................... 124 Configuration of Power Generation Circuit........................................................ 125 Specification of External Elements Connected to HD66789 Power Supply ...... 126 Instruction Setting Flow...................................................................................... 127 Power Supply Setting Flow ................................................................................ 129 Pattern Diagram for Voltage Setting................................................................... 130 Oscillation Circuit ...
Page 4
... HD66789 Conditions on Setting the 1st/2nd Screen Drive Position Register ........................................ 138 Absolute Maximum Values ................................................................................ 140 Electric Characteristics (T.B.D.)......................................................................... 141 DC Characteristics ................................................................................................................. 141 AC Characteristics ................................................................................................................. 142 80-system Bus Interface Timing Characteristics.................................................................... 142 Clock Synchronized Serial Interface Timing Characteristics ................................................ 145 Reset Timing Characteristics (V CC RGB interface timing characteristics ..................................................................................... 147 Liquid crystal driver output characteristics ...
Page 5
... HD66789 Description The HD66789 handles 262,144 TFT colors and can drive a TFT color liquid crystal display of 176 RGB x 240 dots with an incorporated RAM compliant to graphics display of 176 RGB x 240 dots at maximum, and a 528-channel source driver outputs. The HD66789 incorporates a gate driver and a power circuit for driving liquid crystal display to drive a TFT panel with a single chip. The HD66789’ ...
Page 6
... HD66789 Features x Liquid crystal controller/driver for 262,144 TFT-color 176RGB x 240-dot graphics display x Single chip solution for a TFT display panel x System interface – 8-/9-/16-/18-bit high-speed bus interface – Serial Peripheral Interface (SPI) – 8-bit transmission x 3 times (262k/65k color modes) x Interface for moving picture display – ...
Page 7
... HD66789 Block Diagram Vcc Index (IR) Control register (CR IM3-1, IM0/ID CS* System Interface 18 VLD -18 bits -16 bits bits - 8 bits WR*/SCL - clock synchronization RD* serial (SPI) 18 DB0/SDI 3-transmission DB1/SDO, mode ~DB17 RESET* TEST1 TEST2 TS7-0 VciLVL Voltage Vci Adjustment VciOUT circuit Step-up Vci1 circuit 1 ...
Page 8
... ID setting. MPU Select the HD66789. Low: the HD6678 is selected and accessible High: the HD66789 is not selected and not accessible Must be fixed to the GND level while not used. MPU Indicate whether the data is valid or not during RAM write. Low: Valid (Write data to RAM) High: Invalid (Not write data to RAM) RAM address will be updated irrespective of VLD ...
Page 9
... HD66789 Signals Number I/O of Pins WR*/SCL DB0/SDI 1 I/O DB1/SDO 1 I/O DB2~DB17 16 I/O ENABLE 1 I Rev.0.12, May 09 2003, page 9 of 156 Connected Functions to MPU Select register. Low: Index/status, High: Control Fix to the “IOVcc” or “GND” level while using SPI. MPU In 80-system bus interface mode, serves as a write strobe signal. ...
Page 10
... HD66789 Signals Number I/O of Pins ENABLE 1 I VSYNC 1 I HSYNC 1 I DOTCLK 1 I PD0~PD17 18 I RESET S1~S528 528 O G1~G240 240 O Vcom1, Vcom2 2 O Rev.0.12, May 09 2003, page 10 of 156 Connected Functions to MPU EPL ENABLE VLD ...
Page 11
... HD66789 Signals Number I/O of Pins VcomR 1 I VcomH 1 O VcomL 1 O C11+, C11 C12+, C12 C21+, C21- C22+, C22- OSC1, OSC2 FLM 1 O Vci 1 I VciLVL 1 I REGP 1 I/O VciOUT 1 I Vci1 1 I VLOUT1 1 O DDVDH 1 I Rev.0.12, May 09 2003, page 11 of 156 ...
Page 12
... HD66789 Signals Number I/O of Pins VLOUT2 1 O VGH 1 I VLOUT3 1 O VGL 1 I VLOUT4 1 O VCL 1 I VREG1OUT 1 I/O Vcc 1 - IOVcc 1 - RVcc 1 - GND 1 - AGND 1 - RGND 1 - CGND 1 O TEST1 1 I TEST2 1 I Rev.0.12, May 09 2003, page 12 of 156 Connected Functions to Stabilizing Output stepped-up DDVDH voltage, which is stepped up to the capacitor, level Vci1 x 4~6 from the step-up circuit 2 ...
Page 13
... HD66789 Signals Number I/O of Pins V0P, V31P V0N, V31N VGS 1 I VTESTS 1 I/O TS0~TS7 8 O TESTA1 1 I/O TESTA2 1 I/O TESTA4 1 I/O VMONI 1 O IOVccDUM1 IOGNDDUM1 TESTO1 DUMMY - DUMMYR - Rev.0.12, May 09 2003, page 13 of 156 Connected Functions to Stabilizing Output from internal positive polarity operational amplifier when capacitor the operational amplifier is ON (SAP2-0 = “ ...
Page 14
... HD66789 PAD arrangement n Chip size : 22.7mm × 2.80mm (T.B.D.) n Chip thickness : 400µm (typ PAD coordinate : PAD center n Coordinate origin : Chip center n Au bump size : (1) 80µ m × 80µm Corner dummy No.1, No220, No.284, No.937 (2) 54µm×100µ m Input : No.2 ~ No.219 (3) 31µ m×77µ m Laced LCD output side : No ...
Page 15
... HD66789 PAD Coordinate pad No pad name X Y pad No 1 TESTO1 -11214.0 -1264.0 2 DUMMY1 -10888.2 -1254.0 3 Vcom1 -10782.3 -1254.0 4 Vcom1 -10702.1 -1254.0 5 VGH -10569.1 -1254.0 6 VGH -10489.0 -1254.0 7 VLOUT2 -10387.5 -1254.0 8 C22+ -10227.4 -1254.0 9 C22+ -10147.2 -1254.0 10 C22- -10067.1 -1254.0 11 C22- -9986.9 -1254 ...
Page 16
... HD66789 pad No pad name X Y pad No 521 S354 2977.7 1148.5 651 S224 522 S353 2944.6 1265.5 652 S223 523 S352 2911.6 1148.5 653 S222 524 S351 2878.5 1265.5 654 S221 525 S350 2845.4 1148.5 655 S220 526 S349 2812.3 1265.5 656 S219 527 S348 2779 ...
Page 17
... HD66789 BUMP Arrangements S1 ~ S528 G1 ~ G240 I/O pins TESTO1 ~ 4 Rev.0.12, May 09 2003, page 17 of 156 31 35 BUMP 77 40 117 S=2387um S=2387um Unit 100 Min.80 S=5400um Unit S=6400um Unit: um Preliminary ...
Page 18
... The HD66789 has five high-speed system interfaces: 80-system 18-/16-/9-/8-bit bus and Serial Peripheral Interface (SPI) port. The interface mode is selected with IM3-0 pins. The HD66789 has three registers: 16-bit index register (IR), 18-bit write-data register (WDR), and 18-bit read-data register (RDR). The IR stores index information from control registers and GRAM. The WDR temporarily stores data to write into the control registers and GRAM, and the RDR temporarily stores data read from GRAM ...
Page 19
... Bit Operations The HD66789 supports a write data mask function that selects and writes data into GRAM by bit, and performs logical operation or conditional rewrite on the contents of compare registers and the data to write to GRAM. For details, see the “Graphics Operation Functions” section. ...
Page 20
... LCD Driver Circuit The LCD driver circuit of HD66789 consists of a 528-output source driver (S1 ~ S528) and a 240-output gate driver (G1 ~ G240). Display pattern data are latched when 528-bit data arrive. The latched data controls source driver and generates drive waveforms. The gate driver, which operates display scan, selects either VGH or VGL level to output ...
Page 21
... HD66789 GRAM Address MAP SG pin GS=0 GS=1 17 … … … … 0 "0000"H "0001"H G1 G240 G2 G239 "0100"H "0101"H G3 G238 "0200"H "0201"H G4 G237 "0300"H "0301"H "0400"H "0401"H G5 G236 "0500"H "0501"H G6 G235 "0600"H "0601"H G7 G234 G8 G233 "0700"H "0701"H G9 G232 "0800"H " ...
Page 22
... HD66789 80-System 18-Bit Interface GRAM Data RGB Arrangement Output pin S ( 80-System 16-Bit Interface GRAM Data RGB Arrangement S ( Output pin 80-System 9-Bit Interface st 1 Transmission GRAM Data RGB Arrangement ...
Page 23
... HD66789 18-bit RGB interface GRAM Data RGB Arrangement S ( Output pin 16-bit RGB interface GRAM Data RGB Arrangement S ( Output pin 6-bit RGB interface st 1 Transmission GRAM Data RGB R5 R4 ...
Page 24
... HD66789 SG pin GS=0 GS=1 17 … … … … G240 "00AF"H "00AE"H "01AF"H "01AE"H G2 G239 "02AF"H "02AE"H G3 G238 "03AF"H "03AE"H G4 G237 G5 G236 "04AF"H "04AE"H G6 G235 "05AF"H "05AE"H G7 G234 "06AF"H "06AE"H "07AF"H "07AE"H G8 G233 "08AF"H "08AE"H G9 G232 "09AF"H " ...
Page 25
... HD66789 80-system 18-bit interface GRAM Data RGB Arrangement S (528 - 3n) Output pin 80-system 16-bit interface GRAM Data RGB Arrangement S (528 - 3n) Output pin 80-system 9-bit interface GRAM Data RGB Arrangement S (528 - 3n) ...
Page 26
... HD66789 -bit interface (3 transmissions / pixel, 262k color mode : TRI = 1, DFM1 - 0 =10) 80-system Transmission GRAM Data RGB Arrangement S (528 - 3n) Output pin 80-system 8 -bit interface (3 transmissions/pixel, 65k color mode : TRI = 1, DFM1 - Transmission GRAM Data ...
Page 27
... HD66789 18- bit RGB interface GRAM Data RGB Arrangement Output S (528 - 3n) pin 16- bit RGB interface GRAM Data RGB Arrangement S (528 – 3n) Output pin 6- bit RGB interface st 1 Transmission GRAM Data ...
Page 28
... HD66789 Instructions Outline The HD66789 adapts 18-bit bus architecture that enables high-speed interfacing with a high-performance microcomputer. Data sent from external (18/16/9/8 bits) are stored temporarily in the instruction register (IR) and the data register (DR) to store control information before internal operation starts. Since internal operation is decided according to the signal sent from the microcomputer, register selection signal (RS), read/write signal (R/W), and internal 16-bit data bus signal (DB15 to DB0) are called instruction ...
Page 29
... HD66789 80-system 18-bit interface GRAM Data Instruction Bit (IB 80-system 16-bit interface GRAM Data Instruction Bit (IB 80-system 9-bit interface 1 GRAM Data Instruction Bit (IB 80-system 8-bit interface / SPI(2/3 transmissions) ...
Page 30
... HD66789 Status Read The status read instruction reads the internal status of the HD66789. L7–0: Indicate the position of raster-row driving liquid crystal. R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 Start Oscillation (R00h) The start oscillation instruction restarts the oscillator in a halt state during the standby mode. After executing this instruction, wait at least 10 ms for stabilizing oscillation before issuing a next instruction. For details, see the “ ...
Page 31
... HD66789 EPL: Set the polarity of ENABLE pin while using the RGB interface. EPL = “0” : ENABLE = “Low” / Write data to PD17-0. : ENABLE = “High” / Data write invalid. EPL =”1” : ENABLE = “High” / Write data to PD17-0. : ENABLE = “Low” / Data write invalid. ...
Page 32
... HD66789 NL bits NL4 NL3 NL2 NL1 NL0 Display Size Setting disabled 528 x 16 dots 528 x 24 dots 528 x 32 dots 528 x 40 dots 528 x 48 dots 528 x 56 dots ...
Page 33
... The HD66789 modifies write data sent from the microcomputer before writing to GRAM. This enables high-speed GRAM data update, and reduces the load on the microcomputer software. For details, see the “Graphics Operation Function” section. TRI: RAM write data are transmitted in 3 times through 8-bit interface when TRI = 1. When 8-bit interface mode is not selected, set TRI to 0 ...
Page 34
... HD66789 HWM: When HWM=1, data are written to GRAM in high speed. In high-speed write mode, 4 words are written to GRAM in a single operation after executing 4 RAM write operations. If RAM write is terminated before it is executed 4 times, the last data will not be written. Make sure that RAM write is executed 4 times. For this reason, the lower 2 bits must be set to “ ...
Page 35
... HD66789 I/D1-0="00” horizontal : decrement vertical : decrement 0000h AM="0” horizontal EFAFh 0000h AM="1” vertical EFAFh LG2–0: Rewrite data to GRAM after comparing the data that are written by the microcomputer to GRAM with the values in the compare registers (CP17–0) and performing logical operation. For details, see the “ ...
Page 36
... HD66789 Display Control 1 (R07h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 PT1 PT1-0: Determine the kind of source output in a non-display area in the partial display mode. For details, see the “Screen-split drive function” section. PT1-0 bits Source Output for Non-display Area ...
Page 37
... GND level. This reduces the charged/discharged current on LCD, accompanied by the liquid crystal AC drive. When D1-0 = 01, the HD66789 continues the internal display operation, even while the external display is off. When D1-0 = 00, both the internal display operations and the external display operation are halted. ...
Page 38
... HD66789 D1 Source Output 0 0 GND 0 1 GND 1 0 Unlit display 1 1 Display Note 1) Data are written to GRAM from the microcomputer irrespective of the setting of D1-0 bits. Note 2) In the standby mode, D1-0 = "00". However, the D1-0 register setting before entering standby modes is retained. ...
Page 39
... HD66789 FP and BP FP3 FP2 FP1 FP0 Number of lines for the Front Porch BP3 BP2 BP1 BP0 Number of lines for the Back Porch Setting disabled Setting disabled ˜ ˜ ˜ ˜ ...
Page 40
... HD66789 BP3-0, FP3-0 Setting Set BP3-0, FP3-0 bits as follows each in the following operation modes. FLD1 Operation of internal clock FLD1 RGB interface VSYNC interface Display control 3 (R09h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 PTG1-0: Set the gate scan mode when non-display area is driven. ...
Page 41
... HD66789 ISC 3-0: Set the frequency of gate scan when the gate scan mode in the non-display area is set to the interval scan mode with PTG bits. The scan frequency always occurs per odd frames, which is set with ISC bits, and inverted polarity is applied as the gate line is scanned. ...
Page 42
... HD66789 DIV1-0: Set the division ratio of clocks for internal operations (DIV1-0). Internal operations are in synchronization with the clock, the frequency of which is divided according to the DIV1-0 setting. Frame frequency can be adjusted in combination with the adjustment of 1H period (RTN 3-0). When changing the number of drive raster-rows, adjust the frame frequency too. For details, see “Frame Frequency Adjustment Function” ...
Page 43
... HD66789 SDT Bits SDT1 SDT0 Internal Operation (synchronized with the internal operating clock clock clocks clocks clocks Note 1) The amount of delay for the source output is measured from the falling edge of the CL1. 1H period CL1 Source output delay ...
Page 44
... HD66789 1H period CL1 Gn Non-overlap period External Display Interface Control (R0Ch) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 RIM1–0: Specify the RGB I/F mode when the RGB interface is selected. Specifically, this setting specifies the RGB interface mode when it is selected by setting DM and RM bits. The setting must be made before the display operation through the external display interface ...
Page 45
... HD66789 DM1–0:Specify the display operation mode. The interface through which display operation is executed is selected with DM1-0 bits. This setting enables switching between internal clock operation and external display interface. Switching within the external display interface modes (between RGB-I/F and VSYNC- I/F) cannot be made ...
Page 46
... HD66789 Setting for external display interface control allows selecting an optimum interface for the kind of display as follows. When displaying a moving picture (RGB-I/F/VSYNC-I/F), the display data must be written in the high-speed mode (HWM = 1) which enables high-speed RAM access with low power consumption. Display state and interfaces ...
Page 47
... In the VSYNC-I/F mode, only VSYNC input is valid. Other input signals for the external display interface are invalid. The front porch (FP), back porch (BP) periods and display period (NL) are automatically generated in accordance to the frame synchronizing signal (VSYNC) according to the register setting of HD66789. Rev.0.12, May 09 2003, page 47 of 156 Preliminary ...
Page 48
... HD66789 Power Control 1 (R10h) Power Control 2 (R11h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 SAP2 SAP1 SAP0 SAP2-0: Adjust the amount of fixed current from the fixed current source of operational amplifier for the source driver. When the amount of fixed current is set large, the operational amplifier will stabilize, while the current consumption will increase. Select an optimum amount of current taking both the display quality and the current consumption into account. During non-display operation, set SAP2-0 = “ ...
Page 49
... No change is made to the GRAM data or instructions during the sleep mode, although it is retained. STB: When STB = 1, the HD66789 enters into the standby mode. In the standby mode, display operation is completely halted, and all internal operation including the internal R-C oscillator and reception of external clock pulse, is halted. For details, see the “ ...
Page 50
... HD66789 BT2 BT1 BT0 VLOUT1 output (DDVDH Vci1 x 2 [x2 • ª • ª • ª • ª • ª • ª • ª Note 1) The numerals in the bracket [ ] show the step-up scale from Vci1. ...
Page 51
... HD66789 Power Control 3 (R12h) Power Control 4 (R13h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 VCO 0 0 VDV3 VDV2 VDV1 VDV0 W 1 VDV4 MG PON: Start operation of VLOUT3. To stop operation, set PON = 0. To start operation, set PON = 1. VRH3-0: Set the scale for amplifying VLOUT1 voltage (the reference voltage for VCOM and grayscale voltage) ...
Page 52
... HD66789 VRH3 VRH2 VRH1 VRH0 VREG1OUT voltage REGP x 1. REGP x 1. REGP x 1. REGP x 1. REGP x 1. REGP x 1. REGP x 1. halt REGP x 1. REGP x 2.175 REGP x 2.325 ...
Page 53
... HD66789 VcomH VCM4 VCM3 VCM2 VCM1 VCM0 VREG1OUT x 0. VREG1OUT x 0. VREG1OUT x 0. VREG1OUT x 0. VREG1OUT x 0. VREG1OUT x 0.68 Halt internal volume Adjust with a variable external resistor from VcomR ...
Page 54
... HD66789 GRAM Address Range AD15–AD0 GRAM Setting “0000”H – “00AF”H Bitmap data for G1 “0100”H – “01AF”H Bitmap data for G2 “0200”H – “02AF”H Bitmap data for G3 “0300”H – “03AF”H Bitmap data for G4 : “EC00”H – “ECAF”H Bitmap data for G237 “ ...
Page 55
... HD66789 18-bit interface(262,144 colors) INPUT Write Data GRAM RGB Assignment 16-bit interface(65,536 colors) INPUT Write Data GRAM RGB Assignment 9-bit interface (262,144 colors) ...
Page 56
... HD66789 8-bit interface (65,536 colors) TRI = 0, DFM1 Transmission (Upper INPUT Write Data GRAM RGB Assignment 8-bit interface (262,144 colors) TRI =1, DFM1 Transmission INPUT Write Data ...
Page 57
... HD66789 18-bit RGB interface (262,144 colors) INPUT Write Data GRAM RGB Assignment 16-bit RGB interface (65,563 colors) INPUT Write Data GRAM RGB Assignment 6-bit RGB interface (262,144 colors) ...
Page 58
... HD66789 GRAM data settings Grayscale RGB Negative V0 000000 000001 (V0-V1)/2 000010 V1 000011 (V1-V2)/2 000100 V2 (V2-V3)/2 000101 000110 V3 (V3-V4)/2 000111 001000 V4 001001 (V4-V5)/2 001010 V5 001011 (V5-V6)/2 001100 V6 001101 (V6-V7)/2 001110 V7 001111 (V7-V8)/2 010000 V8 010001 (V8-V9)/2 010010 V9 010011 (V9-V10)/2 010100 V10 010101 (V10-V11)/2 010110 V11 010111 (V11-V12)/2 011000 V12 011001 (V12-V13)/2 011010 ...
Page 59
... HD66789 RAM Access through RGB-I/F and System I/F The HD66789 writes all display data on the screens to the internal RAM. This enables the transfer of only the data for the moving picture area as well as for the frames for updating screens through the RGB interface. By writing data in the high speed write mode (HWM = 1) and with the window address function, the HD66789 enables a high-speed access to RAM with low power consumption while displaying moving pictures ...
Page 60
... The second word is read as valid data. When the HD66789 performs an internal bit processing, such as logical operation, the data latched in the read-data latch are used to complete it by single read out operation ...
Page 61
... HD66789 16-bit interface GRAM data Read data Output 9-bit interface GRAM data Read data Output (Upper) 8-bit interface / SPI GRAM ...
Page 62
... First word GRAM Read-data latch Write (data of address n) Second word DB17-0 DB17-0 GRAM Automatic address update: N +α Dummy read (invalid data) First word GRAM Read-data latch Write(data of address n) Second word DB17-0 DB17-0 ii) Logical arithmetic operacion inside HD66789 GRAM read sequence Preliminary GRAM ...
Page 63
... HD66789 RAM Write Data Mask (R23h) RAM Write Data Mask (R24h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 WM17–0: Write-mask the data when they are written to GRAM by bit. For example, if WM17 = 1, the WM17 write-mask the MSB of the data to write to GRAM so that the data in the MSB are not written to GRAM. The rest of WM16-0 bits also write-mask the data in the corresponding bits when these bits are set to “ ...
Page 64
... HD66789 J Control (R30h to R39h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 IB9 R30 R31 R31 R33 R34 R35 R36 R37 R38 R39 PKP52-00 : The J fine adjustment registers for positive polarity ...
Page 65
... HD66789 Gate Scan Position (R40h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 SCN4-0: Specify the position where the gate driver scan starts. Make an optimum setting for the gate driver in use. SC Bits and Gate scan start position SCN4 SCN3 SCN2 ...
Page 66
... HD66789 Vertical Scroll Control (R41h) R/W RS IB15 IB14 IB13 IB12 IB11 IB10 VL7–0: Specify the number of raster-rows that are scrolled and control smooth scrolling in the vertical direction. The number of raster-rows is specified from 0 to 240. The raster-rows of the specified number are scrolled during display. When the 240th raster-row is displayed, the scrolling display starts afresh from the 1st raster-row. The number of raster-rows that are scrolled (VL7– ...
Page 67
... HD66789 SS27–20: Specify the start position for driving the second screen by line. The liquid crystal is driven by from the gate driver of “the set value + 1”. The second screen is driven when SPT = 1. SE27–20: Specify the end position for driving the second screen by line. The liquid crystal is driven by to the gate driver of “ ...
Page 68
... HD66789 Instruction List (T.B.D.) Main Category Sub Category Upper Index Command Index - Index Index SR Status Read Status Read 0* Display Control Oscillation Start 00h Device Code Read 01h Driver Output Control 02h LCD AC driving Control 03h Entry Mode 04h Compare Register (1) 05h Compare Register (2) ...
Page 69
... HD66789 Reset Function The HD66789 makes internal initialization with RESET input. During RESET, the HD66789 busy state, and no instruction from the MPU and access to GRAM are accepted. The time required for the RESET input is at least 1ms. In case of power-on reset, wait at least 10ms after the power is turned on until the R-C oscillation frequency becomes stabilized ...
Page 70
... HD66789 GRAM Data Initialization The data in GRAM are not initialized by the RESET input. Initialize through software during the display OFF (D1–0 = “00”). Initial state of Output Pins a. Liquid crystal driver output pins (source outputs): Output GND level b. Oscillator output pin (OSC2): Outputs oscillation signal Rev ...
Page 71
... GRAM through a system interface, it enables moving pictures display with a system interface. In this case, there are some constraints in the RAM writing speed and method. The HD66789 handles the following 4 operational modes for the type of display. The setting can be made through an external display interface. A transition between the modes must follow the transition flow. ...
Page 72
... System interface System RGB interface Rev.0.12, May 09 2003, page 72 of 156 Display Operation Mode (DM1-0) Internal operating clock (DM1-0 = 00) RGB interface (DM1-0 = 01) RGB interface (DM1-0 = 01) VSYNC interface (DM1-0 = 10) CSn* RS WR* (RD*) DB17-0 18/16/9/8 HD66789 VLD ENABLE VSYNC HSYNC DOTCLK PD17-0 18/16/6 Interfaces and HD66789 Preliminary ...
Page 73
... HD66789 System Interface The following shows the kinds of system interfaces and the IM pins setting for selecting an interface. The instruction setting and RAM access are made through a system interface. IM bits setting and the type of system interface IM3 IM2 IM1 IM0 MPU-Interface Mode ...
Page 74
... HD66789 80-system 18-bit interface 80-system 18-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to IOVcc/GND/IOVcc/GND levels respectively. MPU 18-bit microcomputer and HD66789 Instruction Input Instruction RAM data write Input ...
Page 75
... HD66789 80-system 16-bit interface The 80-system 16-bit parallel data transmission becomes operable by setting IM3/2/1/0 pins to GND/GND/IOVcc/GND levels respectively. H8/2245 16-bit microcomputer and HD66789 Input Instruction Input GRAM write data Rev ...
Page 76
... The unused pins DB8-0 must be fixed to either IOVcc or GND level. When writing into the index register, the upper byte (8 bits) must be written. H8/2254 9-bit microcomputer and HD66789 Instructions 1 st ...
Page 77
... HD66789 Data transmission synchronizing in 9-bit bus interface mode The HD66789 supports a data transmission synchronizing function, which resets the upper/lower counter that counts the number of transmission of upper/lower 9-bit data in the 9-bit bus interface mode. When a discrepancy occurs in the upper/lower 9-bit data transmission due to effects from noise and so on, the “00” ...
Page 78
... The data to write to RAM are expanded into 18 bits internally. The unused pins DB9-0 must be fixed to either IOVcc or GND level. When writing into the index register, the upper byte (8 bits) must be written. H8/2245 8-bit microcomputer and HD66789 Rev.0.12, May 09 2003, page 78 of 156 CSn ...
Page 79
... HD66789 Instruction 1 st Transfer (Upper) Input Instruction RAM data write 1 st Transfer (Upper) Input Write data GRAM RAM data write : TRI =1, DFM1 Transmission st INPUT ...
Page 80
... HD66789 Data transmission synchronizing in 8-bit bus interface mode The HD66789 supports a data transmission synchronizing function, which resets the upper/lower counter that counts the number of transmission of upper/lower 8-bit data in the 8-bit bus interface mode. When a discrepancy occurs in the transmission of upper/lower 8-bit data due to effects from noise and so on, the “ ...
Page 81
... SPI mode, the unused DB15-2 pins must be fixed at either IOVcc or GND level. The HD66789 recognizes the start of data transfer at the falling edge of CS* input to initiate the transfer of start byte. It recognizes the end of data transfer at the rising edge of CS* input. The HD66789 is selected when the 6-bit chip address in the start byte transferred from the transmission device and the 6-bit device identification code assigned to the HD66789 are compared and both 6-bit data correspond ...
Page 82
... HD66789 Transmission (Upper Input D15 D14 D13 D12 D11 D10 D9 Instruction Transmission (Upper Input D15 D14 D13 D12 D11 D10 D9 Write data GRAM Rev.0.12, May 09 2003, page 82 of 156 2 Transmission (Lower ...
Page 83
... HD66789 A)Basic data transmission through SPI Data transmission start CS* (Input) SCL (Input) SDI (Input) “0” “1” “1” “1” “0” ID Device ID code Start byte SDO (Output) B)Consecutive data transmission through SPI CS* (Input ...
Page 84
... HD66789 VSYNC Interface The HD66789 incorporates a VSYNC-I/F, which enables moving picture display with only a system interface and the frame-synchronizing signal (VSYNC). This interface enables moving picture display with minimum modification to a conventional system. LCDC/ MPU The VSYNC-I/F becomes operable by setting DM1 and the VSYNC I/F mode, the internal display operations are synchronized with VSYNC ...
Page 85
... HD66789 The VSYNC-I/F has limits on the minimum speed for RAM write through a system interface and the frequency of the internal clock. It requires RAM write speed more than the result that is calculated from the following formula. Internal clock frequency (fosc) [Hz] = Frame frequency u (Display line (NL) Front porch (FP) Back ...
Page 86
... HD66789 VSYNC RAM write Back porch (14 raster-rows) Display (240 raster-rows) Front porch (2 raster-rows) Blanking period Operation through VSYNC interface Notes to the VSYNC interface 1. The aforementioned example of calculation is just a result of calculation. In the actual settings, causes for the fluctuations of internal clocks and so on should be taken into consideration necessary to make a setting for the RAM write speed with enough margins ...
Page 87
... HD66789 Internal Clock Operation to VSYNC Interface Internal clock operation HWM = Address Setting VSYNC interface mode setting (DM1 Index register set (R22h) Wait more than 1 frame Wait more than 1 frame VSYNC interface Write data to RAM VSYNC interface operation Internal clock mode setting ...
Page 88
... HD66789 External Display Interface The following interfaces are available as the external display interface (RGB interface). The interface is selected by setting RIM1-0 bits. RAM is accessible through the RGB interface. RIM bits setting and RGB interface RIM1 RIM0 RGB Interface 18-bit RGB interface 0 0 16-bit RGB interface ...
Page 89
... HD66789 VLD and ENABLE signals The relationship with the VLD and ENABLE signals is as follows. With the ENABLE signal, the addresses are not updated during data write, while with the VLD signal, the addresses are updated during data write when the ENABLE is “Low”. The polarity of the ENABLE signal is inverted by the setting of EPL bit ...
Page 90
... HD66789 The timing chart of 6-bit RGB interface is as follows. 1 frame Back porch period VSYNC HSYNC DOTCLK ENABLE VLD PD17-0 VSYNC HLW>=3CLK HSYNC 1 clock DOTCLK DTST >= HLW ENABLE VLD PD17-0 Note 1) In 6-bit interface.mode, one pixel, which consists of R,G, and B, must be transmitted in synchronization with 3 DOTCLKs ...
Page 91
... HD66789 Moving picture display The HD66789 incorporates the RGB interface to display moving pictures and RAM to store display data, which provides the following merits in displaying moving pictures. x The window address function enables the transfer of only data for the moving picture area. x The high-speed write mode enables high-speed access to RAM with low power consumption Only transmitting data that are written over the moving picture area ...
Page 92
... GRAM Data transmission synchronization in 6-bit RGB interface mode The HD66789 incorporates a transmission counter to count the first, second, third data transmissions in the 6-bit RBG interface mode. The transmission counter is reset to the first transmission on the falling edge of VSYNC. When a discrepancy occurs in the transmission of first, second and third data, the counter is reset so that a first data transmission will be made at the start of each frame (on the falling edge of VSYNC) and the data transmission restarts in the correct order from the next frame ...
Page 93
... GRAM Rev.0.12, May 09 2003, page 93 of 156 Trans- Trans- Trans- Trans- mission mission mission mission VSYNC HSYNC DOTCLK C HD66789 VLD ENABLE PD17-13 PD12,0 2 GND 16-bit RGB interface ...
Page 94
... The instructions are set only through a system interface. LCDC RAM data Write Input Write data GRAM Rev.0.12, May 09 2003, page 94 of 156 VSYNC HSYNC DOTCLK HD66789 VLD ENABLE PD17-0 18 18-bit RGB interface ...
Page 95
... HD66789 Notes to the external display interface 1. While an external display interface is selected, the following functions are not available. Function External Display Interface Partial display Not available Scroll function Not available Interlaced drive Not available Graphics operation function Not available 2. The VSYNC, HSYNC, and DOTCLK signals must be supplied consecutively during display operation through the RGB-I/F ...
Page 96
... HD66789 Internal Clock Operation to RGB I/F (1) Internal clock operation HWM = Display operation Address Setting in synchronization with the internal clock RGB I/F Setting The value set in DM1-0 and RM (DM1-0=01, RM=1) become valid after the completion of 1-frame display. Index resister setting (R22h) Wait more than 1 frame ...
Page 97
... HD66789 Timing Interfacing with Liquid Crystal Panel Signals The relationship between RGB I/F signals and the liquid crystal panel signals in the RGB I/F mode is as follows. Back porch period (BP) >=1H VSYNC 1H HSYNC DOTCLK ENABLE VLD PD17 5DOTCLK 1H FLM CLW2-0 CL1 SHW1-0 STG2-0 ...
Page 98
... HD66789 The timing interfacing with the liquid crystal panel signals in the internal clock operation mode is as follows. 1H FLM CLW2-0 CL1 SHW1-0 STG2-0 SFTCLK DISPTMG G1 G2 G240 SDT1 S1-528 EQ M (VCOM) Note 1) FLM, CL1, SFTCLK, DISPTMG, EQ, and M are internal signals. ...
Page 99
... HD66789 Scan Mode Setting The shift direction of gate signal is changeable by the combination of SM and GS bit settings. This allows various ways of connecting a liquid crystal panel and the HD66789 raster-rows of odd number raster-rows of odd number Rev.0.12, May 09 2003, page 99 of 156 ...
Page 100
... In the high-speed RAM write mode (HWM), data to write to RAM is temporarily stored to the internal register of HD66789. The data storage in the register is executed by word. When the data storage operation is executed 4 times, all data stored in the register are written to RAM at once. While the data is being written from the register to RAM, another set of data is being written to the register ...
Page 101
... HD66789 CS* (input (input) RAM RAM RAM RAM Index DB15-0 data data data data (R22 (input/output) Upper lower Upper lower RAM address Note : In the high-speed mode (HWM), data are written to the RAM every 4 words. This means in the 8-bit interface mode, ...
Page 102
... HD66789 Comparison between Normal and High-Speed RAM Write Operations Normal RAM Write (HWM=0) Logical operation function Available Compare operation function Available BGR function Available Write mask function Available RAM address set Specified by one word RAM read Read by one word RAM write ...
Page 103
... HD66789 High-Speed RAM Write with Window Address To rewrite the data in an arbitrary rectangular area of RAM consecutively in high speed, the number of RAM access should be made 4 multiple times. Accordingly some window-address range may require dummy write operation to make the RAM access 4 multiple times. The number of dummy write is set when setting the window address as follows ...
Page 104
... HD66789 Writing data in the horizontal direction ID0 = 1 Window address range setting HSA = h12, HEA = h30 VSA = h08, VEA = hA0 High-speed RAM write mode setting HWM = 1 Address set AD = h0810 * Note Dummy RAM write X 2 RAM write X 31 Dummy RAM write X 3 Note: In the high-speed RAM write mode, the address set must be either ID0 bit setting ...
Page 105
... HD66789 Window Address Function The window address function enables consecutive data write within the rectangular window-address area on the on-chip GRAM, which is specified with horizontal address registers (start: HSA7-0, end: HEA 7-0) and vertical address registers (start: VSA7-0, end: VEA7-0). The address transition direction is determined with AM bits (either increment or decrement). Accordingly, the data, including picture data, are written consecutively without taking the data wrap position into consideration ...
Page 106
... HD66789 Graphics Operation Function The HD66789 greatly reduces the load on the graphics-processing software in the microcomputer with the 18-bit bus architecture and the graphics bit operation. The graphics bit operation includes: 1. The write data mask function that selectively rewrites some of the 18-bit write data. ...
Page 107
... The HD66789 expands the 16-bit data sent from the microcomputer into the 18-bit data. In the18-bit interface mode, data are not expanded. The write data mask function of the HD66789 controls the write operation of the 18-bit data from the microcomputer to GRAM by bit. The write data mask function write data in the bits whose corresponding bits in the write data mask resister (WM17– ...
Page 108
... HD66789 2. Write mode LG2–0 = 000 This mode is used when data are vertically written in high-speed mode also used to initialize the graphics RAM (GRAM), develop font patterns or draw a line vertically. The write-data mask function (WM17–0) is also available with this mode. After writing, the address counter (AC) automatically ...
Page 109
... HD66789 3. Write mode LG2–0 = 110/111 This mode is used when data are horizontally written with comparing the write data and the value set in the compare register (CP17– pixel. When the result of the comparison satisfies a condition, the write data sent from the microcomputer are written to GRAM. The write-data mask function (WM17–0) is also available with this mode ...
Page 110
... HD66789 4. Write mode LG2–0 = 110/111 This mode is used when data are horizontally written with comparing the write data and the value set in the compare register (CP17– pixel. When the result of the comparison satisfies a condition, the write data sent from the microcomputer are written to GRAM. The write-data mask function (WM17–0) is also available with this mode ...
Page 111
... HD66789 J-Correction Function The HD66789 incorporates J-correction function to simultaneously display 262,144 colors, by which 8- level grayscale is determined by the gradient-adjustment and fine-adjustment registers. Select either positive or negative polarity of the registers according to the characteristics of a liquid crystal panel. MSB Display data PKP ...
Page 112
... HD66789 Configuration of Grayscale Amplifier The eight levels (VIN0-7) of grayscale are determined by the gradient adjustment and fine adjustment registers. The 8 levels are then divided into 32 levels (V0-31) by the ladder resistors placed between each level. Gradient Adjustment Register PRP/N1 PRP/N0 PKP/ VREG1OUT VGS Rev ...
Page 113
... HD66789 VDH VRP0[3:0] VRP0 0 ~30R RP0 5R RP1 RP2 RP3 4R RP4 RP5 RP6 RP7 VRHP PRP0[2:0] 0 ~28R RP8 RP9 RP10 1R RP11 RP12 RP13 RP14 5R RP15 RP16 RP17 RP18 1R RP19 RP20 RP21 RP22 16R RP23 RP24 RP25 RP26 1R RP27 RP28 RP29 RP30 RP31 ...
Page 114
... HD66789 J-Correction Register The J-adjustment register is a group of registers to set an appropriate grayscale voltage for the J- characteristics of a liquid crystal panel. The register group is categorized into the ones adjusting gradient, amplitude, and fine-tuning in relation to grayscale number and grayscale voltage characteristics. Each register can make an independent setting for the positive/negative polarity. The reference value and RGB are common to both polarities ...
Page 115
... HD66789 J-Correction Registers Register Positive Groups Polarity Gradient PRP0 adjustment PRP1 Amplitude VRP0 adjustment VRP1 Fine adjustment PKP0 PKP1 PKP2 PKP3 PKP4 PKP5 Ladder resistors and 8-to-1 selector Block configuration The block diagram of page 112 consists of two ladder resistors including variable resistors, and 8-to-1 selectors which select the voltage generated by the ladder resistors to output a reference voltage for the grayscale voltage ...
Page 116
... HD66789 8-to-1 selector The 8-to-1 selectors select a voltage level generated by the ladder resistors according to the fine adjustment registers, and output six kinds of reference voltage, VIN1 to VIN 6. The relationship between the fine adjustment register and the selected voltage is as follows. Fine adjustment registers and selected voltage ...
Page 117
... HD66789 The grayscale levels (V0-V31) are calculated according to the following formulas. Formulas for calculating voltage (Positive polarity) (1) Pin VREG1OUT - ∆ V*VRP0/SUMRP KVP0 KVP1 VREG1OUT - ∆ V* VRP0+5R)/SUMRP KVP2 VREG1OUT - ∆ V* VRP0+9R)/SUMRP KVP3 VREG1OUT - ∆ V* VRP0+13R)/SUMRP KVP4 VREG1OUT - ∆ V* VRP0+17R)/SUMRP KVP5 VREG1OUT - ∆ ...
Page 118
... HD66789 Formulas for calculating voltage (Positive polarity) (2) Grayscale Voltage V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 V29 V30 V31 Rev.0.12, May 09 2003, page 118 of 156 ...
Page 119
... HD66789 Formulas for calculating voltage (Negative polarity) (1) Pin Formula VREG1OUT - ∆ V*VRN0/SUMRN KVP0 KVN1 VREG1OUT - ∆ V* VRN0+5R)/SUMRN VREG1OUT - ∆ V* VRN0+9R)/SUMRN KVN 2 VREG1OUT - ∆ V* VRN0+13R)/SUMRN KVN 3 KVN 4 VREG1OUT - ∆ V* VRN0+17R)/SUMRN KVN 5 VREG1OUT - ∆ V* VRN0+21R)/SUMRN KVN 6 VREG1OUT - ∆ V* VRN0+25R)/SUMRN KVN 7 VREG1OUT - ∆ ...
Page 120
... HD66789 Formulas for calculating voltage (Negative polarity) (2) Grayscale Voltage Rev.0.12, May 09 2003, page 120 of 156 Formula V0 VINN0 V1 V4+(VINN1-V4)*(15/24) V2 V4+(VINN1-V4)*(8/24) V3 V4+(VINN1-V4)*(4/24) V4 VINN2 V10+(V4-V10)*(20/24 V10+(V4-V10)*(16/24) V7 V10+(V4-V10)*(12/24) V8 V10+(V4-V10)*(8/24) V20+(V8-V20)*(4/24) V9 VINN3 V10 V11 V21+(V10-V21)*(21/24) V12 ...
Page 121
... HD66789 Relationship between RAM data and output level The relationship between the RAM data and the source output level is as follows. V0 Negative polarity Positive polarity V31 RAM data and the output voltage Sn Vcom Rev.0.12, May 09 2003, page 121 of 156 RAM data ...
Page 122
... HD66789 8-color Display Mode The HD66789 incorporates 8-color display mode. The available grayscale levels are V0 and V31, and the voltages for the other levels (V1-V30) are halted to reduce power consumption. The J-fine-adjustment registers, PKP0-PKP5 and PKN0-PKN5 are not available in the 8-color display mode. Since the power supply for the levels V1-V30 are halted, RGB data in GRAM should be set to either “ ...
Page 123
... HD66789 To switch between the 262, 144-color mode and the 8-color mode, make settings according to the following sequences. 262,144 to 8 colors Display off GON = “1” DTE = “1” D1-0 = “10” Wait (2 frame or more) Display off GON = “1” DTE = “0” ...
Page 124
... The following figure illustrates an example of configuring a TFT-LCD panel of 176x 240 dots withHD66789. Vcom Vcom DCDC Gate Driver Circuit Vci1 Vci RESET System configuration with HD66789 Rev.0.12, May 09 2003, page 124 of 156 176 pixels α TFT G239 G240 S527 S528 ...
Page 125
... HD66789 Configuration of Power Generation Circuit The internal configuration of power generation circuit of HD66789 is as follows. In case of OCG assemby, separate on the FPC. VciLVL Voltage Adjustment Circuit REGP VcomH voltage adjustment Vci (in case of adjusting VciOUT with external VciOUT variable resistors) Output AMP VcomR Vci1 ...
Page 126
... HD66789 Specification of External Elements Connected to HD66789 Power Supply The following table shows specifications of external elements connected to HD66789 power supply. Capacitor Capacity Recommended voltage characteristic) 6V 10V 25V 0 characteristic) 6V Shot-key diode Feature VF < 0.4V / 20mA at 25 centigrade, VR>=30V (recommended diode : HSC226) Variable resistor Feature > ...
Page 127
... HD66789 Instruction Setting Flow Make a setting for each instruction according to the following sequence. Display ON/OFF Display off Display off GON = 1 DTE = 1 D1 Wait (2 frames or more) Display off GON = 1 DTE = 0 D1 Wait (2 frames or more) Display off GON = 0 DTE = 0 D1 Power supply off SAP2-0 = “ ...
Page 128
... HD66789 Standby and Sleep Standby Display off flow Standby set (STB = “1”) Oscillation Start Wait 10 ms Standby canceled (STB = “0”) Power setting Display on low Rev.0.12, May 09 2003, page 128 of 156 Sleep Display off low Standby Sleep set set Sleep set (SLP = “1”) Standby Sleep canceled (SLP = “ ...
Page 129
... HD66789 Power Supply Setting Whenever turning on the power supply, it must be done in accordance to the following procedure. The stabilization time for the oscillation circuits, step-up circuits, and operational amplifiers depends on the external resistors and capacitors. Power supply (Vcc, Vci, IOVcc) ON IOVcc Vci Vcc ...
Page 130
... HD66789 Pattern Diagram for Voltage Setting The following figures are the pattern diagram of voltage setting for the HD66789 and the voltage waveforms. Vci (2.5 ~ 3.3V) VC Vci1 Vcc (2.4 ~ 3.3V) IOVcc (1.8 ~ 3.3V) GND (0V) Pattern diagram for voltage setting Note 1) Voltage drop occurs in relation to set voltage for each DDVDH, VGH, VGL, VCL output depending on current consumption required for each output. (DDVDH+VREG1OUT) > ...
Page 131
... HD66789 Oscillation Circuit The HD66789 generates oscillation by internal R-C oscillator with an external oscillation resistor placed between the OSC1 and OSC2 pins. The oscillation frequency varies depending on the value of external resistor, the distance of wiring, and the power supply voltage for the oscillation. For example, the oscillation frequency becomes low when increasing the value of Rf resistor, or lowering the power supply voltage. See the “ ...
Page 132
... HD66789 n-raster-row Inversion AC Drive The HD66789, in addition to LCD inversion AC drive by frame, supports n-raster-row inversion AC drive where alternation occurs by n raster-rows, where n takes a number between 1 to 64. The n-raster-row inversion AC drive enables to overcome the problems related to display quality. In determining n (the value set in the NW bit +1), the number of raster-rows by which alternation occurs, check the display quality on the actual liquid crystal panel ...
Page 133
... HD66789 Interlaced Drive The HD66789 supports interlaced drive, which divides one frame into n fields and then drives to prevent flickers. To determine the number of fields (n: value set in the FLD bits), check the display quality on the actual liquid crystal panel. The following table shows the gate selection for each number of fields The figure illustrates the output waveforms of the 3-field interlaced drive ...
Page 134
... HD66789 AC Polarity G3n + 1 G3n + 2 G3n + 3 Gate output timing in 3-field interlaced drive Rev.0.12, May 09 2003, page 134 of 156 1 frame Blank period Field 1 Field 2 Field 3 Field 1 Preliminary ...
Page 135
... HD66789 AC Timing The AC timings of frame inversion AC drive, 3-field interlaced drive, and n-raster-row inversion drive are illustrated as follows. In case of frame inversion AC drive, alternation occurs at the completion of drawing one frame, followed by a blank, which lasts for 16H periods. In this case, all outputs from the gate are Vgoff outputs ...
Page 136
... HD66789 Frame-Frequency Adjustment Function The HD66789 incorporates frame frequency adjustment function. The frame frequency during the liquid crystal drive is adjusted by the instruction setting (DIV, RTN) while keeping the oscillation frequency fixed. Setting the oscillation frequency high in advance allows switching the frame frequency in accordance to the kind of displayed picture (i ...
Page 137
... HD66789 Screen -split Drive Function The HD66789 allows selectively driving two screens at arbitrary positions with the screen-drive position registers (R42 and R43). Only the raster-rows required to display two screens at arbitrary positions are selectively driven to reduce power consumption. The first screen drive position register (R42) specifies the start line (SS17-10) and the end line (SE17-10) for displaying the first screen ...
Page 138
... When making settings for the start line (SS17-10) and end line (SE17-10) of the first screen drive position register (R42), and the start line (SS27-20) and end line (SE27-20) of the second screen drive position register (R43) with the HD66789 necessary to satisfy the following conditions to display screens correctly. ...
Page 139
... HD66789 Full screen display Wait for 2 screen or more Partial display ON Full screen display Rev.0.12, May 09 2003, page 139 of 156 PT1 Set SS/SE bits Screen division drive set up flow As required PT1 PT1 PT1 Full screen display Set SS/SE bits setting flow Partial display setting flow ...
Page 140
... HD66789 Absolute Maximum Values Item Symbol Power supply voltage (1) Vcc Power supply voltage (2) Vci - GND Power supply voltage (3) DDVDH - GND Power supply voltage (4) GND -VCL Power supply voltage (5) DDVDH - VCL Power supply voltage (6) VGH - GND Power supply voltage (7) GND - VGL Input voltage ...
Page 141
... HD66789 Electric Characteristics (T.B.D.) DC Characteristics (V = 1 –40 to +85°C CC Item Symbol Unit Test Condition Input high voltage Input low voltage ( (OSC1 pin) Input low voltage ( (Except OSC1 pin) Output high voltage ( OH1 (DB0-17 pins) Output low voltage (1) ...
Page 142
... HD66789 AC Characteristics (V = 1 –40 to +85°C CC Clock Characteristics (V = 1 Item Symbol External clock fcp frequency T.B.D. External clock duty Duty ratio External clock rise time trcp External clock fall time tfcp R-C oscillation clock fOSC 80-system Bus Interface Timing Characteristics Normal Write Mode (HWM=0) (Vcc = 1.8 to 2.4 V) ...
Page 143
... HD66789 High-Speed Write Mode (HWM=1) (Vcc = 1.8 to 2.4 V) Item Bus cycle time Write Read Write low-level pulse width Read low-level pulse width Write high-level pulse width Read high-level pulse width Write/Read rise/fall time Write (RS to CS*, WR*) Set up time T.B.D. Read (RS to CS*, RD*) Address hold time ...
Page 144
... HD66789 High-Speed Write Mode (HWM=1) : Vcc = 2.4 to 3.7 V Item Write Bus cycle time Read Write low-level pulse width Read low-level pulse width Write high -level pulse width Read high -level pulse width T.B.D. Write/Read rise/fall time Write (RS to CS*, WR*) Set up time Read (RS to CS*, RD*) ...
Page 145
... HD66789 Clock Synchronized Serial Interface Timing Characteristics Vcc = 1.8 to 2.4 V Item Write (received) Serial clock cycle time Read (transmitted Write (received) Serial clock high-level pulse Read width T.B.D. (transmitted Write (received) Serial clock low-level pulse Read width (transmitted Serial clock rise/fall time Chip select set up time ...
Page 146
... HD66789 Reset Timing Characteristics (V CC Item Symbol T.B.D. Reset low-level width t RES Reset rise time t rRES Rev.0.12, May 09 2003, page 146 of 156 = 1.8 to 3.7 V) Unit Test Min Condition ms Figure Figure 4 — Preliminary Typ Max — — — 10 ...
Page 147
... HD66789 RGB interface timing characteristics 18/16 bit RGB interface (HWM =1), Vcc = 1.8V to 2.4V Item Symbol VSYNC/HSYNC Set up time tSYNCS ENABLE Set up time ENABLE Hold time VLD Set up time VLD Hold time T.B.D. DOTCLK “Low” Level pulse PWDL width DOTCLK “High” Level pulse PWDH ...
Page 148
... HD66789 6 bit RGB interface (HWM = 1), Vcc = 1.8V to 2.4 V Item VSYNC/HSYNC Set up time ENABLE Set up time ENABLE Hold time VLD Set up time T.B.D. VLD Hold time DOTCLK “Low” Level pulse width DOTCLK “High” Level pulse width DOTCLK cycle time Data Set up time ...
Page 149
... HD66789 Liquid crystal driver output characteristics Item Symbol Unit Driver output tdd Ps delay time T.B.D. Electrical Characteristics Notes 1. For bare die and wafer products, specified up to 85qC. 2. The following three circuits are I pin, I/O pin, O pin configurations. Pins: RESET*, CS*, E/WR, RW/RD, RS, OSC1, OPOFF, IM2-1, IM0/ID,TEST ...
Page 150
... HD66789 5. This excludes the current flowing through output drive MOSs. This excludes the current flowing through the input/output units. The input level must be fixed high or low because through current increases if the CMOS input is left floating. Even if the CS pin is low or high when an access with the interface pin is not performed, current consumption does not change ...
Page 151
... HD66789 T.B.D. OSC1 Rf OSC2 External Resistance Value and R-C Oscillation Frequency (Referential Data) External Resistance Vcc = 1.8 (Rf) V 110 k: 299 150 k: 234 180 k: 202 T.B.D. 200 k: 186 240 k: 160 270 k: 145 300 k: 132 390 k: 106 430 k: 97 11. Applies to the internal oscillator operations using external oscillation resistor Rf (figure and table). ...
Page 152
... HD66789 Load circuits for measuring AC characteristics T.B.D. AC characteristic measuring load circuit Data bus : DB17-DB0, PD17-0 Test Point 50pF 80-system Bus Operation RS T.B.D. CS RD* DB0 to DB1 5 DB0 to DB1 5 Note 1) PWLW and PWLR is specified in the overlapped period when CS* is low and WR* or RD* is low. ...
Page 153
... HD66789 Clock Synchronized Serial Interface Operation Start: S CS* VIL tCSU T.B.D. SCL VIH VIL SDI SDO RESET Operation T.B.D. RESET * VIL Rev.0.12, May 09 2003, page 153 of 156 tSCYC tscf tscr tSCL tSCH VIH VIH VIH VIL VIL VIL tSISU tSIH VIH VIH Input data ...
Page 154
... HD66789 RGB I/F Operation trgbf trgbf VSYNC HSYNC VIH VIL ENABLE T.B.D. VLD trgbf VIH DOTCLK VIH PD17-0 VIL Liquid crystal Driver Output VCOM T.B.D. S1-528 Rev.0.12, May 09 2003, page 154 of 156 tSYNCS VIH VIL tENS tENH VIH VIH VIH VIL VIL VIL tVLS ...
Page 155
... HD66789 Sales Strategic Planning Div. Keep safety first in your circuit designs! 1. Renesas Technology Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. ...
Page 156
... HD66789 Revision Record Rev. Date Contents of Modification 0.1 2003.05.08 First issue Rev.0.12, May 09 2003, page 156 of 156 Preliminary Drawn by Approved by ...