x24f064 Intersil Corporation, x24f064 Datasheet - Page 13

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x24f064

Manufacturer Part Number
x24f064
Description
Serialflash Tm Memory With Block Lock Tm Protection
Manufacturer
Intersil Corporation
Datasheet
X24F064/032/016
The program cycle time is the time from a valid stop
condition of a write sequence to the end of the internal
erase/program cycle. During the program cycle, the
Bus Timing
Notes: (5) Typical values are for T
Guidelines for Calculating Typical Values of
Bus Pull-Up Resistors
Bus Timing
Program Cycle Limits
SDA OUT
SDA
SCL
Symbol
(6) t
SDA IN
t
PR
120
100
SCL
80
60
40
20
time the device requires to automatically complete the internal program operation.
WR
0
(6)
0
is the minimum cycle time to be allowed from the system perspective unless polling techniques are used. It is the maximum
MIN.
RESISTANCE
BUS CAPACITANCE (pF)
20
R MIN =
R MAX =
t SU:STA
MAX.
RESISTANCE
40
WORD n
8th BIT
V CC MAX
I OL MIN
C BUS
Program Cycle Time
60
t R
Parameter
80 100 120
A
= 25 C and nominal supply voltage (2.7V).
=1.2K
t HD:STA
ACK
t F
6686 ILL F19.1
t AA
t HD:DAT
t HIGH
CONDITION
Min.
STOP
13
t LOW
X24F064/032/016 bus interface circuits are disabled,
SDA is allowed to remain HIGH, and the device does
not respond to its slave address.
SYMBOL TABLE
t DH
t SU:DAT
Typ.
t WR
WAVEFORM
5
(5)
CONDITION
START
INPUTS
Must be
steady
May change
from LOW
to HIGH
May change
from HIGH
to LOW
Don’t Care:
Changes
Allowed
N/A
Max.
10
t R
t SU:STO
t BUF
OUTPUTS
Will be
steady
Will change
from LOW
to HIGH
Will change
from HIGH
to LOW
Changing:
State Not
Known
Center Line
is High
Impedance
6686 ILL F18
6686 ILL F17
Units
ms
6686 FRM T11.1

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