hm5216805 Renesas Electronics Corporation., hm5216805 Datasheet - Page 22

• Manufacturer Part Number: hm5216805
• Description: 16 M Lvttl Interface Sdram 100 Mhz/83 Mhz 1-mword 8-bit 2-bank/2-mword 4-bit 2-bank - Hitachi Semiconductor
• Manufacturer: Renesas Electronics Corporation.

HM5216805 Series, HM5216405 Series
Operation of HM5216805 Series, HM5216405 Series
Read/Write Operations
Bank active: Before executing a read or write operation, the corresponding bank and the row address must
be activated by the bank active (ACTV) command. Either bank 0 or bank 1 is activated according to the
status of the A11 pin, and the row address (AX0 to AX10) is activated by the A0 to A10 pins at the bank
active command cycle. An interval of t
following read/write command input.
Read operation: A read operation starts when a read command is input. Output buffer becomes Low-Z in
the (CAS Latency - 1) cycle after read command set. HM5216805 Series, HM5216405 Series can perform
a burst read operation. The burst length can be set to 1, 2, 4, 8 or full-page (512; HM5216805 Series,
1024; HM5216405 Series). The start address for a burst read is specified by the column address (AY0 to
AY8; HM5216805 Series, AY0 to AY9; HM5216405 Series) and the bank select address (A11) at the read
command set cycle. In a read operation, data output starts after the number of cycles specified by the CAS
Latency. The CAS Latency can be set to 1, 2 or 3. When the burst length is 1, 2, 4, or 8, the Dout buffer
automatically becomes High-Z at the next cycle after the successive burst-length data has been output.
When the burst length is full-page (512; HM5216805 Series, 1024; HM5216405 Series), data is
repeatedly output until the burst stop command is input. The CAS latency and burst length must be
specified at the mode register.
CAS Latency
Command
22
Address
Dout
CLK
CL = 1
CL = 2
CL = 3
ACTV
Row
t
RCD
Column
READ
RCD
out 0
is required between the bank active command input and the
out 0
out 1
out 2
out 0
out 1
out 2
out 3
out 1
out 3
out 2
out 3
CL: CAS latency
Burst length = 4