32C87 RENESAS [Renesas Technology Corp], 32C87 Datasheet - Page 79

• Manufacturer Part Number: 32C87
• Description: RENESAS MCU
• Manufacturer: RENESAS [Renesas Technology Corp]

M32C/87 Group (M32C/87, M32C/87A, M32C/87B)
REJ03B0127-0151 Rev.1.51 Jul 31, 2008
Page 79 of 85
Switching Characteristics
(VCC1 = VCC2 = 3.0 to 3.6 V, VSS = 0 V, Topr = -20 to 85°C unless otherwise specified)
Table 5.53
NOTES:
td(BCLK-AD)
th(BCLK-AD)
th(RD-AD)
th(WR-AD)
td(BCLK-CS)
th(BCLK-CS)
th(RD-CS)
th(WR-CS)
td(BCLK-RD)
th(BCLK-RD)
td(BCLK-WR)
th(BCLK-WR)
td(DB-WR)
th(WR-DB)
td(BCLK-ALE)
th(BCLK-ALE)
td(AD-ALE)
th(ALE-AD)
tdz(RD-AD)
1. Values, which depend on BCLK frequency, can be obtained from the following equations.
2. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
3. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
4. Values, which depend on BCLK frequency and external bus cycles, can be obtained from the following equation.
5. tc [ns] is added when recovery cycle is inserted.
Symbol
th(WR-DB) =
th(RD-AD)
th(WR-AD) =
th(RD-CS)
th(WR-CS) =
td(DB-WR) =
td(AD-ALE) =
th(ALE-AD) =
Memory Expansion Mode and Microprocessor Mode (when accessing external
memory space with multiplexed bus)
Address output delay time
Address output hold time (BCLK standard)
Address output hold time (RD standard)
Address output hold time (WR standard)
Chip-select signal output delay time
Chip-select signal output hold time (BCLK standard)
Chip-select signal output hold time (RD standard)
Chip-select signal output hold time (WR standard)
RD signal output delay time
RD signal output hold time
WR signal output delay time
WR signal output hold time
Data output delay time (WR standard)
Data output hold time (WR standard)
ALE signal output delay time (BCLK standard)
ALE signal output hold time (BCLK standard)
ALE signal output delay time (address standard)
ALE signal output hold time (address standard)
Address output float start time
=
=
f(BCLK) × 2
f(BCLK) × 2
f(BCLK) × 2
f(BCLK) × 2
f(BCLK) × 2
f(BCLK) × 2
f(BCLK) × 2
f(BCLK) × 2
10
10
10
9
9
9
10
10
10
10
10
× m
× n
× n
9
9
9
9
9
- 20 [ns]
- 10 [ns]
- 15 [ns]
- 10 [ns]
- 10 [ns]
- 25 [ns] (if external bus cycle is a φ + b φ , m = (b × 2) - 1)
- 20 [ns] (if external bus cycle is a φ + b φ , n = a)
- 20 [ns] (if external bus cycle is a φ + b φ , n = a)
Parameter
(5)
(5)
(5)
(5)
(5)
See Figure 5.2
Measurement
Condition
VCC1 = VCC2 = 3.3 V
5. Electrical Characteristics
(note 1)
(note 1)
(note 1)
(note 1)
(note 2)
(note 1)
(note 3)
(note 4)
Min.
-3
-3
-5
-2
0
Standard
Max.
18
18
18
18
18
8
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns