alc250-lf Realtek Semiconductor Corporation, alc250-lf Datasheet - Page 40

• Manufacturer Part Number: alc250-lf
• Description: Two-channel Ac?97 2.3 Audio Codec With Equalizer
• Manufacturer: Realtek Semiconductor Corporation

9. Design Suggestions
9.1 Clocking
configuration is listed below:
*Low: Pulled low by a 0 ohm resistor. NC: Not connect or pulled high.
*Pin-46is internally pulled high by a weak resistor.
9.2 AC-Link
When the ALC250 receives serial data from the AC97 controller, it samples SDATA_OUT on the falling edge of BIT_CLK.
When the ALC250 sends serial data to the AC97 controller, it starts to drive SDATA_IN on the rising edge of BIT_CLK.
The ALC250 will return any uninstalled bits or registers with 0 for read operations. The ALC250 also stuffs the unimplemented
slot or bit with 0 in SDATA_IN. Note that AC-LINK is MSB-justified.
Refer to “Audio CODEC ’97 Component Specification Revision 2.3.” for details.
9.3 Reset
There are 3 types of reset operations: Cold, Warm and Register.
Cold
Register
Warm
The AC97 controller should drive SYNC and SDATA_OUT low during the period of RESET# assertion to guarantee that the
ALC250 has reset successfully.
Two-Channel AC’97 2.3 Audio Codec
According to AC’97 ver 2.3, the primary mode while RESET# is asserted, if a clock is present at BIT-CLK pin for at least 5
cycles before RESET# is de-asserted, ALC250 is a consumer of BITCLK. ALC250 should use external 12.288MHz BITCLK
as its clock source.
Reset Type
SDATA-OUT
Configuration
Pin-46(XTLSEL)
SDATA-IN
The clock source is decided by XTLSEL latched from pin-46 after power-on reset. The clock source of different
SYNC
Slot#
Default ALC250 Slot Arrangement – CODEC ID = 00 (ALC250 supports only primary mode)
Low
NC
NC
TAG CMD DATA PCM
TAG ADD
Write register indexed 00h
Driven SYNC high for specified period without
BIT_CLK
Assert RESET# for a specified period
0
1
R
DATA PCM
2
Trigger condition
Operation & ID0
ID0
0 (Primary) Output
0 (Primary)
0 (Primary)
3
L
L
PCMR
PCMR
4
BIT-CLK
Output
12.288MHz
12.288MHz
Input
5
6
SPDIF
35
7
L
Clock source
Crystal or ext. 24.576MHz is attached
at XTL-IN
Crystal or ext. 14.318MHz is attached
at XTL-IN
12.288M input at BIT-CLK
SPDIF
R
Reset all hardware logic and all registers to its default
value.
Reset all registers to its default value.
Reactivates AC-LINK, no change to register values.
8
9
10
11
CODEC response
12
ALC250 DataSheet
Rev1.3