alc250-lf Realtek Semiconductor Corporation, alc250-lf Datasheet - Page 35
![no-image](/images/no-image-200.jpg)
alc250-lf
Manufacturer Part Number
alc250-lf
Description
Two-channel Ac?97 2.3 Audio Codec With Equalizer
Manufacturer
Realtek Semiconductor Corporation
Datasheet
1.ALC250-LF.pdf
(47 pages)
- Current page: 35 of 47
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7.2.4 Data Output and Input Timing
7.2.5 Signal Rise and Fall Timing
Two-Channel AC’97 2.3 Audio Codec
Output Valid Delay from rising
edge of BIT_CLK
Note 1: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
Note 2: 50pF external load
Input Setup to falling edge of
BIT_CLK
Input Hold from falling edge of
BIT_CLK
Note: Timing is for SDATA and SYNC outputs with respect to BIT_CLK at the device driving the output.
BIT_CLK combined rise or fall
plus flight time
SDATA combined rise or fall plus
flight time
Note: Combined rise or fall plus flight times are provided for worst case scenario modeling purposes.
BIT_CLK rise time
BIT_CLK fall time
SYNC rise time
SYNC fall time
SDATA_IN rise time
SDATA_IN fall time
SDATA_OUT rise time
SDATA_OUT fall time
Note 1: 75pF external load (50 pF in AC’97 rev2.1)
Note 2: rise is from 10% to 90% of Vdd (V
Note 3: fall is from 90% to 10% of Vdd (V
Parameter
Parameter
Parameter
Parameter
Symbol
Symbol
Symbol
Symbol
Trise
Trise
Tfall
Tfall
Trise
Trise
Tfall
Tfall
t
t
setup
t
hold
Data Output and Input timing diagram
oh
co
ol
BIT_CLK and SYNC timing diagram
sync
dout
sync
dout
clk
din
din
to V
to V
clk
oh
ol
)
)
Minimum
Minimum
Minimum
Minimum
10
10
-
-
-
-
-
-
-
-
-
-
-
30
Typical
Typical
Typical
Typical
-
-
-
-
-
-
-
-
-
-
-
-
-
Maximum
Maximum
Maximum
Maximum
ALC250 DataSheet
15
7
7
6
6
6
6
6
6
6
6
-
-
Units
Units
Units
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Rev1.3
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